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Side by Side Diff: src/IceTargetLoweringMIPS32.cpp

Issue 1948093002: [Subzero][MIPS32] Implement sext, zext and trunc (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addressed review comments Created 4 years, 7 months ago
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1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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898 return; 898 return;
899 } else { 899 } else {
900 _mov(Dest, ReturnReg); 900 _mov(Dest, ReturnReg);
901 } 901 }
902 } 902 }
903 } 903 }
904 } 904 }
905 905
906 void TargetMIPS32::lowerCast(const InstCast *Instr) { 906 void TargetMIPS32::lowerCast(const InstCast *Instr) {
907 InstCast::OpKind CastKind = Instr->getCastKind(); 907 InstCast::OpKind CastKind = Instr->getCastKind();
908 Variable *Dest = Instr->getDest();
909 Operand *Src0 = legalizeUndef(Instr->getSrc(0));
910 const Type DestTy = Dest->getType();
911 const Type Src0Ty = Src0->getType();
912 const uint32_t ShiftAmount =
913 INT32_BITS - (CHAR_BITS * typeWidthInBytes(Src0Ty));
914 ConstantInteger32 *ShiftConstant =
915 llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(ShiftAmount));
916 const uint32_t Mask = (1 << (CHAR_BITS * typeWidthInBytes(Src0Ty))) - 1;
917 ConstantInteger32 *MaskConstant =
918 llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(Mask));
919 ConstantInteger32 *ShiftConstant31 =
920 llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(31));
Jim Stichnoth 2016/05/06 19:55:10 Maybe INT32_BITS-1 ?
sagar.thakur 2016/05/09 11:03:40 Done.
921 ConstantInteger32 *Constant0 =
922 llvm::cast<ConstantInteger32>(Ctx->getConstantZero(IceType_i32));
923
924 if (isVectorType(DestTy) || Src0->getType() == IceType_i1) {
925 UnimplementedLoweringError(this, Instr);
926 return;
927 }
908 switch (CastKind) { 928 switch (CastKind) {
909 default: 929 default:
910 Func->setError("Cast type not supported"); 930 Func->setError("Cast type not supported");
911 return; 931 return;
912 case InstCast::Sext: { 932 case InstCast::Sext: {
913 UnimplementedLoweringError(this, Instr); 933 if (DestTy == IceType_i64) {
934 auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
935 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
936 Variable *Src0R = legalizeToReg(Src0);
937 Variable *T_Lo = I32Reg();
938 if (Src0Ty == IceType_i32) {
939 _mov(DestLo, Src0R);
940 } else if (Src0Ty == IceType_i8) {
Jim Stichnoth 2016/05/06 19:55:09 Combine this and the next clause: else if (Src0
sagar.thakur 2016/05/09 11:03:40 Done. Sorry I didn't notice that.
941 _sll(T_Lo, Src0R, ShiftConstant);
942 _sra(DestLo, T_Lo, ShiftConstant);
943 } else if (Src0Ty == IceType_i16) {
944 _sll(T_Lo, Src0R, ShiftConstant);
945 _sra(DestLo, T_Lo, ShiftConstant);
946 }
947 _sra(DestHi, DestLo, ShiftConstant31);
948 } else {
949 Variable *Src0R = legalizeToReg(Src0);
950 Variable *T = makeReg(DestTy);
951 if (Src0Ty == IceType_i8) {
952 _sll(T, Src0R, ShiftConstant);
953 _sra(Dest, T, ShiftConstant);
954 } else if (Src0Ty == IceType_i16) {
955 _sll(T, Src0R, ShiftConstant);
956 _sra(Dest, T, ShiftConstant);
957 }
958 }
914 break; 959 break;
915 } 960 }
916 case InstCast::Zext: { 961 case InstCast::Zext: {
917 UnimplementedLoweringError(this, Instr); 962 if (DestTy == IceType_i64) {
963 auto *DestLo = llvm::cast<Variable>(loOperand(Dest));
964 auto *DestHi = llvm::cast<Variable>(hiOperand(Dest));
965 Variable *Src0R = legalizeToReg(Src0);
966
967 switch (Src0Ty) {
968 default: { assert(Src0Ty != IceType_i64); } break;
969 case IceType_i32: {
970 _mov(DestLo, Src0R);
971 } break;
972 case IceType_i8: {
973 _andi(DestLo, Src0R, MaskConstant);
974 } break;
975 case IceType_i16: {
976 _andi(DestLo, Src0R, MaskConstant);
977 } break;
978 }
979
980 auto *Zero = getZero();
981 _addiu(DestHi, Zero, Constant0);
982 } else {
983 Variable *Src0R = legalizeToReg(Src0);
984 Variable *T = makeReg(DestTy);
985 if (Src0Ty == IceType_i8)
986 _andi(T, Src0R, MaskConstant);
987 else if (Src0Ty == IceType_i16)
988 _andi(T, Src0R, MaskConstant);
989 _mov(Dest, T);
990 }
918 break; 991 break;
919 } 992 }
920 case InstCast::Trunc: { 993 case InstCast::Trunc: {
921 UnimplementedLoweringError(this, Instr); 994 if (Src0Ty == IceType_i64)
995 Src0 = loOperand(Src0);
996 Variable *Src0R = legalizeToReg(Src0);
997 Variable *T = makeReg(DestTy);
998 _mov(T, Src0R);
999 _mov(Dest, T);
922 break; 1000 break;
923 } 1001 }
924 case InstCast::Fptrunc: 1002 case InstCast::Fptrunc:
925 UnimplementedLoweringError(this, Instr); 1003 UnimplementedLoweringError(this, Instr);
926 break; 1004 break;
927 case InstCast::Fpext: { 1005 case InstCast::Fpext: {
928 UnimplementedLoweringError(this, Instr); 1006 UnimplementedLoweringError(this, Instr);
929 break; 1007 break;
930 } 1008 }
931 case InstCast::Fptosi: 1009 case InstCast::Fptosi:
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1374 // Also try the inverse and use MVN if possible. 1452 // Also try the inverse and use MVN if possible.
1375 // Do a movw/movt to a register. 1453 // Do a movw/movt to a register.
1376 Variable *Reg; 1454 Variable *Reg;
1377 if (RegNum.hasValue()) 1455 if (RegNum.hasValue())
1378 Reg = getPhysicalRegister(RegNum); 1456 Reg = getPhysicalRegister(RegNum);
1379 else 1457 else
1380 Reg = makeReg(Ty, RegNum); 1458 Reg = makeReg(Ty, RegNum);
1381 if (isInt<16>(int32_t(Value))) { 1459 if (isInt<16>(int32_t(Value))) {
1382 Variable *Zero = getPhysicalRegister(RegMIPS32::Reg_ZERO, Ty); 1460 Variable *Zero = getPhysicalRegister(RegMIPS32::Reg_ZERO, Ty);
1383 Context.insert<InstFakeDef>(Zero); 1461 Context.insert<InstFakeDef>(Zero);
1384 _addiu(Reg, Zero, Value); 1462 _addiu(Reg, Zero, C32);
1385 } else { 1463 } else {
1386 uint32_t UpperBits = (Value >> 16) & 0xFFFF; 1464 uint32_t UpperBits = (Value >> 16) & 0xFFFF;
1387 (void)UpperBits; 1465 (void)UpperBits;
1388 uint32_t LowerBits = Value & 0xFFFF; 1466 uint32_t LowerBits = Value & 0xFFFF;
1389 Variable *TReg = makeReg(Ty, RegNum); 1467 Variable *TReg = makeReg(Ty, RegNum);
1390 _lui(TReg, UpperBits); 1468 _lui(TReg, UpperBits);
1391 _ori(Reg, TReg, LowerBits); 1469 _ori(Reg, TReg, LowerBits);
1392 } 1470 }
1393 return Reg; 1471 return Reg;
1394 } 1472 }
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1421 Str << "\t.set\t" 1499 Str << "\t.set\t"
1422 << "nomips16\n"; 1500 << "nomips16\n";
1423 } 1501 }
1424 1502
1425 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM]; 1503 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
1426 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM]; 1504 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
1427 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM]; 1505 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
1428 1506
1429 } // end of namespace MIPS32 1507 } // end of namespace MIPS32
1430 } // end of namespace Ice 1508 } // end of namespace Ice
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