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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. | 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. |
| 6 #if defined(TARGET_ARCH_ARM) | 6 #if defined(TARGET_ARCH_ARM) |
| 7 | 7 |
| 8 #include "vm/flow_graph_compiler.h" | 8 #include "vm/flow_graph_compiler.h" |
| 9 | 9 |
| 10 #include "lib/error.h" | 10 #include "lib/error.h" |
| (...skipping 717 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 728 } | 728 } |
| 729 AllocateRegistersLocally(instr); | 729 AllocateRegistersLocally(instr); |
| 730 } else if (instr->MayThrow() && | 730 } else if (instr->MayThrow() && |
| 731 (CurrentTryIndex() != CatchClauseNode::kInvalidTryIndex)) { | 731 (CurrentTryIndex() != CatchClauseNode::kInvalidTryIndex)) { |
| 732 // Optimized try-block: Sync locals to fixed stack locations. | 732 // Optimized try-block: Sync locals to fixed stack locations. |
| 733 EmitTrySync(instr, CurrentTryIndex()); | 733 EmitTrySync(instr, CurrentTryIndex()); |
| 734 } | 734 } |
| 735 } | 735 } |
| 736 | 736 |
| 737 | 737 |
| 738 // TODO(regis): Pass an offset instead of an Address to avoid addressing | 738 void FlowGraphCompiler::EmitTrySyncMove(intptr_t dest_offset, |
| 739 // mode restrictions and remove Operand::Equals() on IA32/X64 and | |
| 740 // Address::Equals() on ARM/MIPS. | |
| 741 void FlowGraphCompiler::EmitTrySyncMove(Address dest, | |
| 742 Location loc, | 739 Location loc, |
| 743 bool* push_emitted) { | 740 bool* push_emitted) { |
| 744 if (loc.IsConstant()) { | 741 if (loc.IsConstant()) { |
| 745 if (!*push_emitted) { | 742 if (!*push_emitted) { |
| 746 __ Push(R0); | 743 __ Push(R0); |
| 747 *push_emitted = true; | 744 *push_emitted = true; |
| 748 } | 745 } |
| 749 __ LoadObject(R0, loc.constant()); | 746 __ LoadObject(R0, loc.constant()); |
| 750 __ str(R0, dest); | 747 __ StoreToOffset(kWord, R0, FP, dest_offset); |
| 751 } else if (loc.IsRegister()) { | 748 } else if (loc.IsRegister()) { |
| 752 if (*push_emitted && (loc.reg() == R0)) { | 749 if (*push_emitted && (loc.reg() == R0)) { |
| 753 __ ldr(R0, Address(SP, 0)); | 750 __ ldr(R0, Address(SP, 0)); |
| 754 __ str(R0, dest); | 751 __ StoreToOffset(kWord, R0, FP, dest_offset); |
| 755 } else { | 752 } else { |
| 756 __ str(loc.reg(), dest); | 753 __ StoreToOffset(kWord, loc.reg(), FP, dest_offset); |
| 757 } | 754 } |
| 758 } else { | 755 } else { |
| 759 Address src = loc.ToStackSlotAddress(); | 756 const intptr_t src_offset = loc.ToStackSlotOffset(); |
| 760 if (!src.Equals(dest)) { | 757 if (src_offset != dest_offset) { |
| 761 if (!*push_emitted) { | 758 if (!*push_emitted) { |
| 762 __ Push(R0); | 759 __ Push(R0); |
| 763 *push_emitted = true; | 760 *push_emitted = true; |
| 764 } | 761 } |
| 765 __ ldr(R0, src); | 762 __ LoadFromOffset(kWord, R0, FP, src_offset); |
| 766 __ str(R0, dest); | 763 __ StoreToOffset(kWord, R0, FP, dest_offset); |
| 767 } | 764 } |
| 768 } | 765 } |
| 769 } | 766 } |
| 770 | 767 |
| 771 | 768 |
| 772 void FlowGraphCompiler::EmitTrySync(Instruction* instr, intptr_t try_index) { | 769 void FlowGraphCompiler::EmitTrySync(Instruction* instr, intptr_t try_index) { |
| 773 ASSERT(is_optimizing()); | 770 ASSERT(is_optimizing()); |
| 774 Environment* env = instr->env(); | 771 Environment* env = instr->env(); |
| 775 CatchBlockEntryInstr* catch_block = | 772 CatchBlockEntryInstr* catch_block = |
| 776 flow_graph().graph_entry()->GetCatchEntry(try_index); | 773 flow_graph().graph_entry()->GetCatchEntry(try_index); |
| 777 const GrowableArray<Definition*>* idefs = catch_block->initial_definitions(); | 774 const GrowableArray<Definition*>* idefs = catch_block->initial_definitions(); |
| 778 // Parameters. | 775 // Parameters. |
| 779 intptr_t i = 0; | 776 intptr_t i = 0; |
| 780 bool push_emitted = false; | 777 bool push_emitted = false; |
| 781 const intptr_t num_non_copied_params = flow_graph().num_non_copied_params(); | 778 const intptr_t num_non_copied_params = flow_graph().num_non_copied_params(); |
| 782 const intptr_t param_base = | 779 const intptr_t param_base = |
| 783 kParamEndSlotFromFp + num_non_copied_params; | 780 kParamEndSlotFromFp + num_non_copied_params; |
| 784 for (; i < num_non_copied_params; ++i) { | 781 for (; i < num_non_copied_params; ++i) { |
| 785 if ((*idefs)[i]->IsConstant()) continue; // Common constants | 782 if ((*idefs)[i]->IsConstant()) continue; // Common constants |
| 786 Location loc = env->LocationAt(i); | 783 Location loc = env->LocationAt(i); |
| 787 Address dest(FP, (param_base - i) * kWordSize); | 784 EmitTrySyncMove((param_base - i) * kWordSize, loc, &push_emitted); |
| 788 EmitTrySyncMove(dest, loc, &push_emitted); | |
| 789 } | 785 } |
| 790 | 786 |
| 791 // Process locals. Skip exception_var and stacktrace_var. | 787 // Process locals. Skip exception_var and stacktrace_var. |
| 792 CatchEntryInstr* catch_entry = catch_block->next()->AsCatchEntry(); | 788 CatchEntryInstr* catch_entry = catch_block->next()->AsCatchEntry(); |
| 793 intptr_t local_base = kFirstLocalSlotFromFp + num_non_copied_params; | 789 intptr_t local_base = kFirstLocalSlotFromFp + num_non_copied_params; |
| 794 intptr_t ex_idx = local_base - catch_entry->exception_var().index(); | 790 intptr_t ex_idx = local_base - catch_entry->exception_var().index(); |
| 795 intptr_t st_idx = local_base - catch_entry->stacktrace_var().index(); | 791 intptr_t st_idx = local_base - catch_entry->stacktrace_var().index(); |
| 796 for (; i < flow_graph().variable_count(); ++i) { | 792 for (; i < flow_graph().variable_count(); ++i) { |
| 797 if (i == ex_idx || i == st_idx) continue; | 793 if (i == ex_idx || i == st_idx) continue; |
| 798 if ((*idefs)[i]->IsConstant()) continue; | 794 if ((*idefs)[i]->IsConstant()) continue; |
| 799 Location loc = env->LocationAt(i); | 795 Location loc = env->LocationAt(i); |
| 800 Address dest(FP, (local_base - i) * kWordSize); | 796 EmitTrySyncMove((local_base - i) * kWordSize, loc, &push_emitted); |
| 801 EmitTrySyncMove(dest, loc, &push_emitted); | |
| 802 // Update safepoint bitmap to indicate that the target location | 797 // Update safepoint bitmap to indicate that the target location |
| 803 // now contains a pointer. | 798 // now contains a pointer. |
| 804 instr->locs()->stack_bitmap()->Set(i - num_non_copied_params, true); | 799 instr->locs()->stack_bitmap()->Set(i - num_non_copied_params, true); |
| 805 } | 800 } |
| 806 if (push_emitted) { | 801 if (push_emitted) { |
| 807 __ Pop(R0); | 802 __ Pop(R0); |
| 808 } | 803 } |
| 809 } | 804 } |
| 810 | 805 |
| 811 | 806 |
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| 1696 void ParallelMoveResolver::EmitMove(int index) { | 1691 void ParallelMoveResolver::EmitMove(int index) { |
| 1697 MoveOperands* move = moves_[index]; | 1692 MoveOperands* move = moves_[index]; |
| 1698 const Location source = move->src(); | 1693 const Location source = move->src(); |
| 1699 const Location destination = move->dest(); | 1694 const Location destination = move->dest(); |
| 1700 | 1695 |
| 1701 if (source.IsRegister()) { | 1696 if (source.IsRegister()) { |
| 1702 if (destination.IsRegister()) { | 1697 if (destination.IsRegister()) { |
| 1703 __ mov(destination.reg(), ShifterOperand(source.reg())); | 1698 __ mov(destination.reg(), ShifterOperand(source.reg())); |
| 1704 } else { | 1699 } else { |
| 1705 ASSERT(destination.IsStackSlot()); | 1700 ASSERT(destination.IsStackSlot()); |
| 1706 __ str(source.reg(), destination.ToStackSlotAddress()); | 1701 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1702 __ StoreToOffset(kWord, source.reg(), FP, dest_offset); |
| 1707 } | 1703 } |
| 1708 } else if (source.IsStackSlot()) { | 1704 } else if (source.IsStackSlot()) { |
| 1709 if (destination.IsRegister()) { | 1705 if (destination.IsRegister()) { |
| 1710 __ ldr(destination.reg(), source.ToStackSlotAddress()); | 1706 const intptr_t source_offset = source.ToStackSlotOffset(); |
| 1707 __ LoadFromOffset(kWord, destination.reg(), FP, source_offset); |
| 1711 } else { | 1708 } else { |
| 1712 ASSERT(destination.IsStackSlot()); | 1709 ASSERT(destination.IsStackSlot()); |
| 1713 MoveMemoryToMemory(destination.ToStackSlotAddress(), | 1710 const intptr_t source_offset = source.ToStackSlotOffset(); |
| 1714 source.ToStackSlotAddress()); | 1711 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1712 __ LoadFromOffset(kWord, TMP, FP, source_offset); |
| 1713 __ StoreToOffset(kWord, TMP, FP, dest_offset); |
| 1715 } | 1714 } |
| 1716 } else if (source.IsFpuRegister()) { | 1715 } else if (source.IsFpuRegister()) { |
| 1717 if (destination.IsFpuRegister()) { | 1716 if (destination.IsFpuRegister()) { |
| 1718 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); | 1717 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); |
| 1719 DRegister src = EvenDRegisterOf(source.fpu_reg()); | 1718 DRegister src = EvenDRegisterOf(source.fpu_reg()); |
| 1720 __ vmovd(dst, src); | 1719 __ vmovd(dst, src); |
| 1721 } else { | 1720 } else { |
| 1722 if (destination.IsDoubleStackSlot()) { | 1721 if (destination.IsDoubleStackSlot()) { |
| 1722 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1723 DRegister src = EvenDRegisterOf(source.fpu_reg()); | 1723 DRegister src = EvenDRegisterOf(source.fpu_reg()); |
| 1724 __ vstrd(src, destination.ToStackSlotAddress()); | 1724 __ StoreDToOffset(src, FP, dest_offset); |
| 1725 } else { | 1725 } else { |
| 1726 ASSERT(destination.IsQuadStackSlot()); | 1726 ASSERT(destination.IsQuadStackSlot()); |
| 1727 UNIMPLEMENTED(); | 1727 UNIMPLEMENTED(); |
| 1728 } | 1728 } |
| 1729 } | 1729 } |
| 1730 } else if (source.IsDoubleStackSlot()) { | 1730 } else if (source.IsDoubleStackSlot()) { |
| 1731 if (destination.IsFpuRegister()) { | 1731 if (destination.IsFpuRegister()) { |
| 1732 const intptr_t dest_offset = source.ToStackSlotOffset(); |
| 1732 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); | 1733 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); |
| 1733 __ vldrd(dst, source.ToStackSlotAddress()); | 1734 __ LoadDFromOffset(dst, FP, dest_offset); |
| 1734 } else { | 1735 } else { |
| 1735 ASSERT(destination.IsDoubleStackSlot()); | 1736 ASSERT(destination.IsDoubleStackSlot()); |
| 1736 __ vldrd(DTMP, source.ToStackSlotAddress()); | 1737 const intptr_t source_offset = source.ToStackSlotOffset(); |
| 1737 __ vstrd(DTMP, destination.ToStackSlotAddress()); | 1738 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1739 __ LoadDFromOffset(DTMP, FP, source_offset); |
| 1740 __ StoreDToOffset(DTMP, FP, dest_offset); |
| 1738 } | 1741 } |
| 1739 } else if (source.IsQuadStackSlot()) { | 1742 } else if (source.IsQuadStackSlot()) { |
| 1740 UNIMPLEMENTED(); | 1743 UNIMPLEMENTED(); |
| 1741 } else { | 1744 } else { |
| 1742 ASSERT(source.IsConstant()); | 1745 ASSERT(source.IsConstant()); |
| 1743 if (destination.IsRegister()) { | 1746 if (destination.IsRegister()) { |
| 1744 const Object& constant = source.constant(); | 1747 const Object& constant = source.constant(); |
| 1745 __ LoadObject(destination.reg(), constant); | 1748 __ LoadObject(destination.reg(), constant); |
| 1746 } else { | 1749 } else { |
| 1747 ASSERT(destination.IsStackSlot()); | 1750 ASSERT(destination.IsStackSlot()); |
| 1748 StoreObject(destination.ToStackSlotAddress(), source.constant()); | 1751 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1752 __ LoadObject(TMP, source.constant()); |
| 1753 __ StoreToOffset(kWord, TMP, FP, dest_offset); |
| 1749 } | 1754 } |
| 1750 } | 1755 } |
| 1751 | 1756 |
| 1752 move->Eliminate(); | 1757 move->Eliminate(); |
| 1753 } | 1758 } |
| 1754 | 1759 |
| 1755 | 1760 |
| 1756 void ParallelMoveResolver::EmitSwap(int index) { | 1761 void ParallelMoveResolver::EmitSwap(int index) { |
| 1757 MoveOperands* move = moves_[index]; | 1762 MoveOperands* move = moves_[index]; |
| 1758 const Location source = move->src(); | 1763 const Location source = move->src(); |
| 1759 const Location destination = move->dest(); | 1764 const Location destination = move->dest(); |
| 1760 | 1765 |
| 1761 if (source.IsRegister() && destination.IsRegister()) { | 1766 if (source.IsRegister() && destination.IsRegister()) { |
| 1762 ASSERT(source.reg() != IP); | 1767 ASSERT(source.reg() != IP); |
| 1763 ASSERT(destination.reg() != IP); | 1768 ASSERT(destination.reg() != IP); |
| 1764 __ mov(IP, ShifterOperand(source.reg())); | 1769 __ mov(IP, ShifterOperand(source.reg())); |
| 1765 __ mov(source.reg(), ShifterOperand(destination.reg())); | 1770 __ mov(source.reg(), ShifterOperand(destination.reg())); |
| 1766 __ mov(destination.reg(), ShifterOperand(IP)); | 1771 __ mov(destination.reg(), ShifterOperand(IP)); |
| 1767 } else if (source.IsRegister() && destination.IsStackSlot()) { | 1772 } else if (source.IsRegister() && destination.IsStackSlot()) { |
| 1768 Exchange(source.reg(), destination.ToStackSlotAddress()); | 1773 Exchange(source.reg(), destination.ToStackSlotOffset()); |
| 1769 } else if (source.IsStackSlot() && destination.IsRegister()) { | 1774 } else if (source.IsStackSlot() && destination.IsRegister()) { |
| 1770 Exchange(destination.reg(), source.ToStackSlotAddress()); | 1775 Exchange(destination.reg(), source.ToStackSlotOffset()); |
| 1771 } else if (source.IsStackSlot() && destination.IsStackSlot()) { | 1776 } else if (source.IsStackSlot() && destination.IsStackSlot()) { |
| 1772 Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress()); | 1777 Exchange(source.ToStackSlotOffset(), destination.ToStackSlotOffset()); |
| 1773 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { | 1778 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { |
| 1774 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); | 1779 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); |
| 1775 DRegister src = EvenDRegisterOf(source.fpu_reg()); | 1780 DRegister src = EvenDRegisterOf(source.fpu_reg()); |
| 1776 __ vmovd(DTMP, src); | 1781 __ vmovd(DTMP, src); |
| 1777 __ vmovd(src, dst); | 1782 __ vmovd(src, dst); |
| 1778 __ vmovd(dst, DTMP); | 1783 __ vmovd(dst, DTMP); |
| 1779 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { | 1784 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { |
| 1780 ASSERT(destination.IsDoubleStackSlot() || | 1785 ASSERT(destination.IsDoubleStackSlot() || |
| 1781 destination.IsQuadStackSlot() || | 1786 destination.IsQuadStackSlot() || |
| 1782 source.IsDoubleStackSlot() || | 1787 source.IsDoubleStackSlot() || |
| 1783 source.IsQuadStackSlot()); | 1788 source.IsQuadStackSlot()); |
| 1784 bool double_width = destination.IsDoubleStackSlot() || | 1789 bool double_width = destination.IsDoubleStackSlot() || |
| 1785 source.IsDoubleStackSlot(); | 1790 source.IsDoubleStackSlot(); |
| 1786 QRegister qreg = source.IsFpuRegister() ? source.fpu_reg() | 1791 QRegister qreg = source.IsFpuRegister() ? source.fpu_reg() |
| 1787 : destination.fpu_reg(); | 1792 : destination.fpu_reg(); |
| 1788 DRegister reg = EvenDRegisterOf(qreg); | 1793 DRegister reg = EvenDRegisterOf(qreg); |
| 1789 const Address& slot_address = source.IsFpuRegister() | 1794 const intptr_t slot_offset = source.IsFpuRegister() |
| 1790 ? destination.ToStackSlotAddress() | 1795 ? destination.ToStackSlotOffset() |
| 1791 : source.ToStackSlotAddress(); | 1796 : source.ToStackSlotOffset(); |
| 1792 | 1797 |
| 1793 if (double_width) { | 1798 if (double_width) { |
| 1794 __ vldrd(DTMP, slot_address); | 1799 __ LoadDFromOffset(DTMP, FP, slot_offset); |
| 1795 __ vstrd(reg, slot_address); | 1800 __ StoreDToOffset(reg, FP, slot_offset); |
| 1796 __ vmovd(reg, DTMP); | 1801 __ vmovd(reg, DTMP); |
| 1797 } else { | 1802 } else { |
| 1798 UNIMPLEMENTED(); | 1803 UNIMPLEMENTED(); |
| 1799 } | 1804 } |
| 1800 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) { | 1805 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) { |
| 1801 const Address& source_slot_address = source.ToStackSlotAddress(); | 1806 const intptr_t source_offset = source.ToStackSlotOffset(); |
| 1802 const Address& destination_slot_address = destination.ToStackSlotAddress(); | 1807 const intptr_t dest_offset = destination.ToStackSlotOffset(); |
| 1803 | 1808 |
| 1804 ScratchFpuRegisterScope ensure_scratch(this, QTMP); | 1809 ScratchFpuRegisterScope ensure_scratch(this, QTMP); |
| 1805 DRegister scratch = EvenDRegisterOf(ensure_scratch.reg()); | 1810 DRegister scratch = EvenDRegisterOf(ensure_scratch.reg()); |
| 1806 __ vldrd(DTMP, source_slot_address); | 1811 __ LoadDFromOffset(DTMP, FP, source_offset); |
| 1807 __ vldrd(scratch, destination_slot_address); | 1812 __ LoadDFromOffset(scratch, FP, dest_offset); |
| 1808 __ vstrd(DTMP, destination_slot_address); | 1813 __ StoreDToOffset(DTMP, FP, dest_offset); |
| 1809 __ vstrd(scratch, source_slot_address); | 1814 __ StoreDToOffset(scratch, FP, source_offset); |
| 1810 } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) { | 1815 } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) { |
| 1811 UNIMPLEMENTED(); | 1816 UNIMPLEMENTED(); |
| 1812 } else { | 1817 } else { |
| 1813 UNREACHABLE(); | 1818 UNREACHABLE(); |
| 1814 } | 1819 } |
| 1815 | 1820 |
| 1816 // The swap of source and destination has executed a move from source to | 1821 // The swap of source and destination has executed a move from source to |
| 1817 // destination. | 1822 // destination. |
| 1818 move->Eliminate(); | 1823 move->Eliminate(); |
| 1819 | 1824 |
| (...skipping 17 matching lines...) Expand all Loading... |
| 1837 __ str(IP, dst); | 1842 __ str(IP, dst); |
| 1838 } | 1843 } |
| 1839 | 1844 |
| 1840 | 1845 |
| 1841 void ParallelMoveResolver::StoreObject(const Address& dst, const Object& obj) { | 1846 void ParallelMoveResolver::StoreObject(const Address& dst, const Object& obj) { |
| 1842 __ LoadObject(IP, obj); | 1847 __ LoadObject(IP, obj); |
| 1843 __ str(IP, dst); | 1848 __ str(IP, dst); |
| 1844 } | 1849 } |
| 1845 | 1850 |
| 1846 | 1851 |
| 1852 // Do not call or implement this function. Instead, use the form below that |
| 1853 // uses an offset from the frame pointer instead of an Address. |
| 1847 void ParallelMoveResolver::Exchange(Register reg, const Address& mem) { | 1854 void ParallelMoveResolver::Exchange(Register reg, const Address& mem) { |
| 1848 ASSERT(reg != IP); | 1855 UNREACHABLE(); |
| 1849 __ mov(IP, ShifterOperand(reg)); | |
| 1850 __ ldr(reg, mem); | |
| 1851 __ str(IP, mem); | |
| 1852 } | 1856 } |
| 1853 | 1857 |
| 1854 | 1858 |
| 1859 // Do not call or implement this function. Instead, use the form below that |
| 1860 // uses offsets from the frame pointer instead of Addresses. |
| 1855 void ParallelMoveResolver::Exchange(const Address& mem1, const Address& mem2) { | 1861 void ParallelMoveResolver::Exchange(const Address& mem1, const Address& mem2) { |
| 1856 ScratchRegisterScope ensure_scratch(this, IP); | 1862 UNREACHABLE(); |
| 1857 __ ldr(ensure_scratch.reg(), mem1); | |
| 1858 __ ldr(IP, mem2); | |
| 1859 __ str(ensure_scratch.reg(), mem2); | |
| 1860 __ str(IP, mem1); | |
| 1861 } | 1863 } |
| 1862 | 1864 |
| 1863 | 1865 |
| 1866 void ParallelMoveResolver::Exchange(Register reg, intptr_t stack_offset) { |
| 1867 __ mov(TMP, ShifterOperand(reg)); |
| 1868 __ LoadFromOffset(kWord, reg, FP, stack_offset); |
| 1869 __ StoreToOffset(kWord, TMP, FP, stack_offset); |
| 1870 } |
| 1871 |
| 1872 |
| 1873 void ParallelMoveResolver::Exchange(intptr_t stack_offset1, |
| 1874 intptr_t stack_offset2) { |
| 1875 ScratchRegisterScope ensure_scratch(this, IP); |
| 1876 __ LoadFromOffset(kWord, ensure_scratch.reg(), FP, stack_offset1); |
| 1877 __ LoadFromOffset(kWord, TMP, FP, stack_offset2); |
| 1878 __ StoreToOffset(kWord, ensure_scratch.reg(), FP, stack_offset2); |
| 1879 __ StoreToOffset(kWord, TMP, FP, stack_offset1); |
| 1880 } |
| 1881 |
| 1882 |
| 1864 void ParallelMoveResolver::SpillScratch(Register reg) { | 1883 void ParallelMoveResolver::SpillScratch(Register reg) { |
| 1865 __ Push(reg); | 1884 __ Push(reg); |
| 1866 } | 1885 } |
| 1867 | 1886 |
| 1868 | 1887 |
| 1869 void ParallelMoveResolver::RestoreScratch(Register reg) { | 1888 void ParallelMoveResolver::RestoreScratch(Register reg) { |
| 1870 __ Pop(reg); | 1889 __ Pop(reg); |
| 1871 } | 1890 } |
| 1872 | 1891 |
| 1873 | 1892 |
| 1874 void ParallelMoveResolver::SpillFpuScratch(FpuRegister reg) { | 1893 void ParallelMoveResolver::SpillFpuScratch(FpuRegister reg) { |
| 1875 DRegister dreg = EvenDRegisterOf(reg); | 1894 DRegister dreg = EvenDRegisterOf(reg); |
| 1876 __ vstrd(dreg, Address(SP, -kDoubleSize, Address::PreIndex)); | 1895 __ vstrd(dreg, Address(SP, -kDoubleSize, Address::PreIndex)); |
| 1877 } | 1896 } |
| 1878 | 1897 |
| 1879 | 1898 |
| 1880 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) { | 1899 void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) { |
| 1881 DRegister dreg = EvenDRegisterOf(reg); | 1900 DRegister dreg = EvenDRegisterOf(reg); |
| 1882 __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex)); | 1901 __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex)); |
| 1883 } | 1902 } |
| 1884 | 1903 |
| 1885 | 1904 |
| 1886 #undef __ | 1905 #undef __ |
| 1887 | 1906 |
| 1888 } // namespace dart | 1907 } // namespace dart |
| 1889 | 1908 |
| 1890 #endif // defined TARGET_ARCH_ARM | 1909 #endif // defined TARGET_ARCH_ARM |
| OLD | NEW |