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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_IA32. | 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_IA32. |
| 6 #if defined(TARGET_ARCH_IA32) | 6 #if defined(TARGET_ARCH_IA32) |
| 7 | 7 |
| 8 #include "vm/flow_graph_compiler.h" | 8 #include "vm/flow_graph_compiler.h" |
| 9 | 9 |
| 10 #include "lib/error.h" | 10 #include "lib/error.h" |
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| 767 __ LoadObject(EAX, loc.constant()); | 767 __ LoadObject(EAX, loc.constant()); |
| 768 __ movl(dest, EAX); | 768 __ movl(dest, EAX); |
| 769 } else if (loc.IsRegister()) { | 769 } else if (loc.IsRegister()) { |
| 770 if (*push_emitted && loc.reg() == EAX) { | 770 if (*push_emitted && loc.reg() == EAX) { |
| 771 __ movl(EAX, Address(ESP, 0)); | 771 __ movl(EAX, Address(ESP, 0)); |
| 772 __ movl(dest, EAX); | 772 __ movl(dest, EAX); |
| 773 } else { | 773 } else { |
| 774 __ movl(dest, loc.reg()); | 774 __ movl(dest, loc.reg()); |
| 775 } | 775 } |
| 776 } else { | 776 } else { |
| 777 Address src = loc.ToStackSlotAddress(); | 777 const Address& src = Address::StackSlotAddress(loc); |
| 778 if (!src.Equals(dest)) { | 778 if (!src.Equals(dest)) { |
| 779 if (!*push_emitted) { | 779 if (!*push_emitted) { |
| 780 __ pushl(EAX); | 780 __ pushl(EAX); |
| 781 *push_emitted = true; | 781 *push_emitted = true; |
| 782 } | 782 } |
| 783 __ movl(EAX, src); | 783 __ movl(EAX, src); |
| 784 __ movl(dest, EAX); | 784 __ movl(dest, EAX); |
| 785 } | 785 } |
| 786 } | 786 } |
| 787 } | 787 } |
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| 1721 void ParallelMoveResolver::EmitMove(int index) { | 1721 void ParallelMoveResolver::EmitMove(int index) { |
| 1722 MoveOperands* move = moves_[index]; | 1722 MoveOperands* move = moves_[index]; |
| 1723 const Location source = move->src(); | 1723 const Location source = move->src(); |
| 1724 const Location destination = move->dest(); | 1724 const Location destination = move->dest(); |
| 1725 | 1725 |
| 1726 if (source.IsRegister()) { | 1726 if (source.IsRegister()) { |
| 1727 if (destination.IsRegister()) { | 1727 if (destination.IsRegister()) { |
| 1728 __ movl(destination.reg(), source.reg()); | 1728 __ movl(destination.reg(), source.reg()); |
| 1729 } else { | 1729 } else { |
| 1730 ASSERT(destination.IsStackSlot()); | 1730 ASSERT(destination.IsStackSlot()); |
| 1731 __ movl(destination.ToStackSlotAddress(), source.reg()); | 1731 __ movl(Address::StackSlotAddress(destination), source.reg()); |
| 1732 } | 1732 } |
| 1733 } else if (source.IsStackSlot()) { | 1733 } else if (source.IsStackSlot()) { |
| 1734 if (destination.IsRegister()) { | 1734 if (destination.IsRegister()) { |
| 1735 __ movl(destination.reg(), source.ToStackSlotAddress()); | 1735 __ movl(destination.reg(), Address::StackSlotAddress(source)); |
| 1736 } else { | 1736 } else { |
| 1737 ASSERT(destination.IsStackSlot()); | 1737 ASSERT(destination.IsStackSlot()); |
| 1738 MoveMemoryToMemory(destination.ToStackSlotAddress(), | 1738 MoveMemoryToMemory(Address::StackSlotAddress(destination), |
| 1739 source.ToStackSlotAddress()); | 1739 Address::StackSlotAddress(source)); |
| 1740 } | 1740 } |
| 1741 } else if (source.IsFpuRegister()) { | 1741 } else if (source.IsFpuRegister()) { |
| 1742 if (destination.IsFpuRegister()) { | 1742 if (destination.IsFpuRegister()) { |
| 1743 // Optimization manual recommends using MOVAPS for register | 1743 // Optimization manual recommends using MOVAPS for register |
| 1744 // to register moves. | 1744 // to register moves. |
| 1745 __ movaps(destination.fpu_reg(), source.fpu_reg()); | 1745 __ movaps(destination.fpu_reg(), source.fpu_reg()); |
| 1746 } else { | 1746 } else { |
| 1747 if (destination.IsDoubleStackSlot()) { | 1747 if (destination.IsDoubleStackSlot()) { |
| 1748 __ movsd(destination.ToStackSlotAddress(), source.fpu_reg()); | 1748 __ movsd(Address::StackSlotAddress(destination), source.fpu_reg()); |
| 1749 } else { | 1749 } else { |
| 1750 ASSERT(destination.IsQuadStackSlot()); | 1750 ASSERT(destination.IsQuadStackSlot()); |
| 1751 __ movups(destination.ToStackSlotAddress(), source.fpu_reg()); | 1751 __ movups(Address::StackSlotAddress(destination), source.fpu_reg()); |
| 1752 } | 1752 } |
| 1753 } | 1753 } |
| 1754 } else if (source.IsDoubleStackSlot()) { | 1754 } else if (source.IsDoubleStackSlot()) { |
| 1755 if (destination.IsFpuRegister()) { | 1755 if (destination.IsFpuRegister()) { |
| 1756 __ movsd(destination.fpu_reg(), source.ToStackSlotAddress()); | 1756 __ movsd(destination.fpu_reg(), Address::StackSlotAddress(source)); |
| 1757 } else { | 1757 } else { |
| 1758 ASSERT(destination.IsDoubleStackSlot()); | 1758 ASSERT(destination.IsDoubleStackSlot()); |
| 1759 __ movsd(XMM0, source.ToStackSlotAddress()); | 1759 __ movsd(XMM0, Address::StackSlotAddress(source)); |
| 1760 __ movsd(destination.ToStackSlotAddress(), XMM0); | 1760 __ movsd(Address::StackSlotAddress(destination), XMM0); |
| 1761 } | 1761 } |
| 1762 } else if (source.IsQuadStackSlot()) { | 1762 } else if (source.IsQuadStackSlot()) { |
| 1763 if (destination.IsFpuRegister()) { | 1763 if (destination.IsFpuRegister()) { |
| 1764 __ movups(destination.fpu_reg(), source.ToStackSlotAddress()); | 1764 __ movups(destination.fpu_reg(), Address::StackSlotAddress(source)); |
| 1765 } else { | 1765 } else { |
| 1766 ASSERT(destination.IsQuadStackSlot()); | 1766 ASSERT(destination.IsQuadStackSlot()); |
| 1767 __ movups(XMM0, source.ToStackSlotAddress()); | 1767 __ movups(XMM0, Address::StackSlotAddress(source)); |
| 1768 __ movups(destination.ToStackSlotAddress(), XMM0); | 1768 __ movups(Address::StackSlotAddress(destination), XMM0); |
| 1769 } | 1769 } |
| 1770 } else { | 1770 } else { |
| 1771 ASSERT(source.IsConstant()); | 1771 ASSERT(source.IsConstant()); |
| 1772 if (destination.IsRegister()) { | 1772 if (destination.IsRegister()) { |
| 1773 const Object& constant = source.constant(); | 1773 const Object& constant = source.constant(); |
| 1774 if (constant.IsSmi() && (Smi::Cast(constant).Value() == 0)) { | 1774 if (constant.IsSmi() && (Smi::Cast(constant).Value() == 0)) { |
| 1775 __ xorl(destination.reg(), destination.reg()); | 1775 __ xorl(destination.reg(), destination.reg()); |
| 1776 } else { | 1776 } else { |
| 1777 __ LoadObject(destination.reg(), constant); | 1777 __ LoadObject(destination.reg(), constant); |
| 1778 } | 1778 } |
| 1779 } else { | 1779 } else { |
| 1780 ASSERT(destination.IsStackSlot()); | 1780 ASSERT(destination.IsStackSlot()); |
| 1781 StoreObject(destination.ToStackSlotAddress(), source.constant()); | 1781 StoreObject(Address::StackSlotAddress(destination), source.constant()); |
| 1782 } | 1782 } |
| 1783 } | 1783 } |
| 1784 | 1784 |
| 1785 move->Eliminate(); | 1785 move->Eliminate(); |
| 1786 } | 1786 } |
| 1787 | 1787 |
| 1788 | 1788 |
| 1789 void ParallelMoveResolver::EmitSwap(int index) { | 1789 void ParallelMoveResolver::EmitSwap(int index) { |
| 1790 MoveOperands* move = moves_[index]; | 1790 MoveOperands* move = moves_[index]; |
| 1791 const Location source = move->src(); | 1791 const Location source = move->src(); |
| 1792 const Location destination = move->dest(); | 1792 const Location destination = move->dest(); |
| 1793 | 1793 |
| 1794 if (source.IsRegister() && destination.IsRegister()) { | 1794 if (source.IsRegister() && destination.IsRegister()) { |
| 1795 __ xchgl(destination.reg(), source.reg()); | 1795 __ xchgl(destination.reg(), source.reg()); |
| 1796 } else if (source.IsRegister() && destination.IsStackSlot()) { | 1796 } else if (source.IsRegister() && destination.IsStackSlot()) { |
| 1797 Exchange(source.reg(), destination.ToStackSlotAddress()); | 1797 Exchange(source.reg(), Address::StackSlotAddress(destination)); |
| 1798 } else if (source.IsStackSlot() && destination.IsRegister()) { | 1798 } else if (source.IsStackSlot() && destination.IsRegister()) { |
| 1799 Exchange(destination.reg(), source.ToStackSlotAddress()); | 1799 Exchange(destination.reg(), Address::StackSlotAddress(source)); |
| 1800 } else if (source.IsStackSlot() && destination.IsStackSlot()) { | 1800 } else if (source.IsStackSlot() && destination.IsStackSlot()) { |
| 1801 Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress()); | 1801 Exchange(Address::StackSlotAddress(destination), |
| 1802 Address::StackSlotAddress(source)); |
| 1802 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { | 1803 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { |
| 1803 __ movaps(XMM0, source.fpu_reg()); | 1804 __ movaps(XMM0, source.fpu_reg()); |
| 1804 __ movaps(source.fpu_reg(), destination.fpu_reg()); | 1805 __ movaps(source.fpu_reg(), destination.fpu_reg()); |
| 1805 __ movaps(destination.fpu_reg(), XMM0); | 1806 __ movaps(destination.fpu_reg(), XMM0); |
| 1806 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { | 1807 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { |
| 1807 ASSERT(destination.IsDoubleStackSlot() || | 1808 ASSERT(destination.IsDoubleStackSlot() || |
| 1808 destination.IsQuadStackSlot() || | 1809 destination.IsQuadStackSlot() || |
| 1809 source.IsDoubleStackSlot() || | 1810 source.IsDoubleStackSlot() || |
| 1810 source.IsQuadStackSlot()); | 1811 source.IsQuadStackSlot()); |
| 1811 bool double_width = destination.IsDoubleStackSlot() || | 1812 bool double_width = destination.IsDoubleStackSlot() || |
| 1812 source.IsDoubleStackSlot(); | 1813 source.IsDoubleStackSlot(); |
| 1813 XmmRegister reg = source.IsFpuRegister() ? source.fpu_reg() | 1814 XmmRegister reg = source.IsFpuRegister() ? source.fpu_reg() |
| 1814 : destination.fpu_reg(); | 1815 : destination.fpu_reg(); |
| 1815 const Address& slot_address = source.IsFpuRegister() | 1816 const Address& slot_address = source.IsFpuRegister() |
| 1816 ? destination.ToStackSlotAddress() | 1817 ? Address::StackSlotAddress(destination) |
| 1817 : source.ToStackSlotAddress(); | 1818 : Address::StackSlotAddress(source); |
| 1818 | 1819 |
| 1819 if (double_width) { | 1820 if (double_width) { |
| 1820 __ movsd(XMM0, slot_address); | 1821 __ movsd(XMM0, slot_address); |
| 1821 __ movsd(slot_address, reg); | 1822 __ movsd(slot_address, reg); |
| 1822 } else { | 1823 } else { |
| 1823 __ movups(XMM0, slot_address); | 1824 __ movups(XMM0, slot_address); |
| 1824 __ movups(slot_address, reg); | 1825 __ movups(slot_address, reg); |
| 1825 } | 1826 } |
| 1826 __ movaps(reg, XMM0); | 1827 __ movaps(reg, XMM0); |
| 1827 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) { | 1828 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) { |
| 1828 const Address& source_slot_address = source.ToStackSlotAddress(); | 1829 const Address& source_slot_address = Address::StackSlotAddress(source); |
| 1829 const Address& destination_slot_address = destination.ToStackSlotAddress(); | 1830 const Address& destination_slot_address = |
| 1831 Address::StackSlotAddress(destination); |
| 1830 | 1832 |
| 1831 ScratchFpuRegisterScope ensure_scratch(this, XMM0); | 1833 ScratchFpuRegisterScope ensure_scratch(this, XMM0); |
| 1832 __ movsd(XMM0, source_slot_address); | 1834 __ movsd(XMM0, source_slot_address); |
| 1833 __ movsd(ensure_scratch.reg(), destination_slot_address); | 1835 __ movsd(ensure_scratch.reg(), destination_slot_address); |
| 1834 __ movsd(destination_slot_address, XMM0); | 1836 __ movsd(destination_slot_address, XMM0); |
| 1835 __ movsd(source_slot_address, ensure_scratch.reg()); | 1837 __ movsd(source_slot_address, ensure_scratch.reg()); |
| 1836 } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) { | 1838 } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) { |
| 1837 const Address& source_slot_address = source.ToStackSlotAddress(); | 1839 const Address& source_slot_address = Address::StackSlotAddress(source); |
| 1838 const Address& destination_slot_address = destination.ToStackSlotAddress(); | 1840 const Address& destination_slot_address = |
| 1841 Address::StackSlotAddress(destination); |
| 1839 | 1842 |
| 1840 ScratchFpuRegisterScope ensure_scratch(this, XMM0); | 1843 ScratchFpuRegisterScope ensure_scratch(this, XMM0); |
| 1841 __ movups(XMM0, source_slot_address); | 1844 __ movups(XMM0, source_slot_address); |
| 1842 __ movups(ensure_scratch.reg(), destination_slot_address); | 1845 __ movups(ensure_scratch.reg(), destination_slot_address); |
| 1843 __ movups(destination_slot_address, XMM0); | 1846 __ movups(destination_slot_address, XMM0); |
| 1844 __ movups(source_slot_address, ensure_scratch.reg()); | 1847 __ movups(source_slot_address, ensure_scratch.reg()); |
| 1845 } else { | 1848 } else { |
| 1846 UNREACHABLE(); | 1849 UNREACHABLE(); |
| 1847 } | 1850 } |
| 1848 | 1851 |
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| 1921 __ movups(reg, Address(ESP, 0)); | 1924 __ movups(reg, Address(ESP, 0)); |
| 1922 __ addl(ESP, Immediate(kFpuRegisterSize)); | 1925 __ addl(ESP, Immediate(kFpuRegisterSize)); |
| 1923 } | 1926 } |
| 1924 | 1927 |
| 1925 | 1928 |
| 1926 #undef __ | 1929 #undef __ |
| 1927 | 1930 |
| 1928 } // namespace dart | 1931 } // namespace dart |
| 1929 | 1932 |
| 1930 #endif // defined TARGET_ARCH_IA32 | 1933 #endif // defined TARGET_ARCH_IA32 |
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