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Issue 19464002: Replaces Location::ToStackSlotAddress() with Location::ToStackSlotOffset() (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/flow_graph_compiler.h" 8 #include "vm/flow_graph_compiler.h"
9 9
10 #include "lib/error.h" 10 #include "lib/error.h"
(...skipping 738 matching lines...) Expand 10 before | Expand all | Expand 10 after
749 __ LoadObject(R0, loc.constant()); 749 __ LoadObject(R0, loc.constant());
750 __ str(R0, dest); 750 __ str(R0, dest);
751 } else if (loc.IsRegister()) { 751 } else if (loc.IsRegister()) {
752 if (*push_emitted && (loc.reg() == R0)) { 752 if (*push_emitted && (loc.reg() == R0)) {
753 __ ldr(R0, Address(SP, 0)); 753 __ ldr(R0, Address(SP, 0));
754 __ str(R0, dest); 754 __ str(R0, dest);
755 } else { 755 } else {
756 __ str(loc.reg(), dest); 756 __ str(loc.reg(), dest);
757 } 757 }
758 } else { 758 } else {
759 Address src = loc.ToStackSlotAddress(); 759 const Address& src = Address::StackSlotAddress(loc);
760 if (!src.Equals(dest)) { 760 if (!src.Equals(dest)) {
761 if (!*push_emitted) { 761 if (!*push_emitted) {
762 __ Push(R0); 762 __ Push(R0);
763 *push_emitted = true; 763 *push_emitted = true;
764 } 764 }
765 __ ldr(R0, src); 765 __ ldr(R0, src);
766 __ str(R0, dest); 766 __ str(R0, dest);
767 } 767 }
768 } 768 }
769 } 769 }
(...skipping 874 matching lines...) Expand 10 before | Expand all | Expand 10 after
1644 assembler()->vcmpd(dleft, dright); 1644 assembler()->vcmpd(dleft, dright);
1645 assembler()->vmstat(); 1645 assembler()->vmstat();
1646 assembler()->LoadObject(result, Bool::False()); 1646 assembler()->LoadObject(result, Bool::False());
1647 Label done; 1647 Label done;
1648 assembler()->b(&done, VS); // NaN -> false. 1648 assembler()->b(&done, VS); // NaN -> false.
1649 assembler()->LoadObject(result, Bool::True(), true_condition); 1649 assembler()->LoadObject(result, Bool::True(), true_condition);
1650 assembler()->Bind(&done); 1650 assembler()->Bind(&done);
1651 } 1651 }
1652 1652
1653 1653
1654 // Do not implement or use this function. 1654 // Do not implement or use this function.
regis 2013/07/17 16:35:19 The 4 functions below should also be part of a sim
1655 FieldAddress FlowGraphCompiler::ElementAddressForIntIndex(intptr_t cid, 1655 FieldAddress FlowGraphCompiler::ElementAddressForIntIndex(intptr_t cid,
1656 intptr_t index_scale, 1656 intptr_t index_scale,
1657 Register array, 1657 Register array,
1658 intptr_t index) { 1658 intptr_t index) {
1659 UNREACHABLE(); 1659 UNREACHABLE();
1660 return FieldAddress(array, index); 1660 return FieldAddress(array, index);
1661 } 1661 }
1662 1662
1663 1663
1664 // Do not implement or use this function. 1664 // Do not implement or use this function.
(...skipping 31 matching lines...) Expand 10 before | Expand all | Expand 10 after
1696 void ParallelMoveResolver::EmitMove(int index) { 1696 void ParallelMoveResolver::EmitMove(int index) {
1697 MoveOperands* move = moves_[index]; 1697 MoveOperands* move = moves_[index];
1698 const Location source = move->src(); 1698 const Location source = move->src();
1699 const Location destination = move->dest(); 1699 const Location destination = move->dest();
1700 1700
1701 if (source.IsRegister()) { 1701 if (source.IsRegister()) {
1702 if (destination.IsRegister()) { 1702 if (destination.IsRegister()) {
1703 __ mov(destination.reg(), ShifterOperand(source.reg())); 1703 __ mov(destination.reg(), ShifterOperand(source.reg()));
1704 } else { 1704 } else {
1705 ASSERT(destination.IsStackSlot()); 1705 ASSERT(destination.IsStackSlot());
1706 __ str(source.reg(), destination.ToStackSlotAddress()); 1706 __ str(source.reg(), Address::StackSlotAddress(destination));
1707 } 1707 }
1708 } else if (source.IsStackSlot()) { 1708 } else if (source.IsStackSlot()) {
1709 if (destination.IsRegister()) { 1709 if (destination.IsRegister()) {
1710 __ ldr(destination.reg(), source.ToStackSlotAddress()); 1710 __ ldr(destination.reg(), Address::StackSlotAddress(source));
1711 } else { 1711 } else {
1712 ASSERT(destination.IsStackSlot()); 1712 ASSERT(destination.IsStackSlot());
1713 MoveMemoryToMemory(destination.ToStackSlotAddress(), 1713 MoveMemoryToMemory(Address::StackSlotAddress(destination),
1714 source.ToStackSlotAddress()); 1714 Address::StackSlotAddress(source));
1715 } 1715 }
1716 } else if (source.IsFpuRegister()) { 1716 } else if (source.IsFpuRegister()) {
1717 if (destination.IsFpuRegister()) { 1717 if (destination.IsFpuRegister()) {
1718 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); 1718 DRegister dst = EvenDRegisterOf(destination.fpu_reg());
1719 DRegister src = EvenDRegisterOf(source.fpu_reg()); 1719 DRegister src = EvenDRegisterOf(source.fpu_reg());
1720 __ vmovd(dst, src); 1720 __ vmovd(dst, src);
1721 } else { 1721 } else {
1722 if (destination.IsDoubleStackSlot()) { 1722 if (destination.IsDoubleStackSlot()) {
1723 DRegister src = EvenDRegisterOf(source.fpu_reg()); 1723 DRegister src = EvenDRegisterOf(source.fpu_reg());
1724 __ vstrd(src, destination.ToStackSlotAddress()); 1724 __ vstrd(src, Address::StackSlotAddress(destination));
1725 } else { 1725 } else {
1726 ASSERT(destination.IsQuadStackSlot()); 1726 ASSERT(destination.IsQuadStackSlot());
1727 UNIMPLEMENTED(); 1727 UNIMPLEMENTED();
1728 } 1728 }
1729 } 1729 }
1730 } else if (source.IsDoubleStackSlot()) { 1730 } else if (source.IsDoubleStackSlot()) {
1731 if (destination.IsFpuRegister()) { 1731 if (destination.IsFpuRegister()) {
1732 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); 1732 DRegister dst = EvenDRegisterOf(destination.fpu_reg());
1733 __ vldrd(dst, source.ToStackSlotAddress()); 1733 __ vldrd(dst, Address::StackSlotAddress(source));
1734 } else { 1734 } else {
1735 ASSERT(destination.IsDoubleStackSlot()); 1735 ASSERT(destination.IsDoubleStackSlot());
1736 __ vldrd(DTMP, source.ToStackSlotAddress()); 1736 __ vldrd(DTMP, Address::StackSlotAddress(source));
1737 __ vstrd(DTMP, destination.ToStackSlotAddress()); 1737 __ vstrd(DTMP, Address::StackSlotAddress(destination));
1738 } 1738 }
1739 } else if (source.IsQuadStackSlot()) { 1739 } else if (source.IsQuadStackSlot()) {
1740 UNIMPLEMENTED(); 1740 UNIMPLEMENTED();
1741 } else { 1741 } else {
1742 ASSERT(source.IsConstant()); 1742 ASSERT(source.IsConstant());
1743 if (destination.IsRegister()) { 1743 if (destination.IsRegister()) {
1744 const Object& constant = source.constant(); 1744 const Object& constant = source.constant();
1745 __ LoadObject(destination.reg(), constant); 1745 __ LoadObject(destination.reg(), constant);
1746 } else { 1746 } else {
1747 ASSERT(destination.IsStackSlot()); 1747 ASSERT(destination.IsStackSlot());
1748 StoreObject(destination.ToStackSlotAddress(), source.constant()); 1748 StoreObject(Address::StackSlotAddress(destination), source.constant());
1749 } 1749 }
1750 } 1750 }
1751 1751
1752 move->Eliminate(); 1752 move->Eliminate();
1753 } 1753 }
1754 1754
1755 1755
1756 void ParallelMoveResolver::EmitSwap(int index) { 1756 void ParallelMoveResolver::EmitSwap(int index) {
1757 MoveOperands* move = moves_[index]; 1757 MoveOperands* move = moves_[index];
1758 const Location source = move->src(); 1758 const Location source = move->src();
1759 const Location destination = move->dest(); 1759 const Location destination = move->dest();
1760 1760
1761 if (source.IsRegister() && destination.IsRegister()) { 1761 if (source.IsRegister() && destination.IsRegister()) {
1762 ASSERT(source.reg() != IP); 1762 ASSERT(source.reg() != IP);
1763 ASSERT(destination.reg() != IP); 1763 ASSERT(destination.reg() != IP);
1764 __ mov(IP, ShifterOperand(source.reg())); 1764 __ mov(IP, ShifterOperand(source.reg()));
1765 __ mov(source.reg(), ShifterOperand(destination.reg())); 1765 __ mov(source.reg(), ShifterOperand(destination.reg()));
1766 __ mov(destination.reg(), ShifterOperand(IP)); 1766 __ mov(destination.reg(), ShifterOperand(IP));
1767 } else if (source.IsRegister() && destination.IsStackSlot()) { 1767 } else if (source.IsRegister() && destination.IsStackSlot()) {
1768 Exchange(source.reg(), destination.ToStackSlotAddress()); 1768 Exchange(source.reg(), Address::StackSlotAddress(destination));
1769 } else if (source.IsStackSlot() && destination.IsRegister()) { 1769 } else if (source.IsStackSlot() && destination.IsRegister()) {
1770 Exchange(destination.reg(), source.ToStackSlotAddress()); 1770 Exchange(destination.reg(), Address::StackSlotAddress(source));
1771 } else if (source.IsStackSlot() && destination.IsStackSlot()) { 1771 } else if (source.IsStackSlot() && destination.IsStackSlot()) {
1772 Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress()); 1772 Exchange(Address::StackSlotAddress(destination),
1773 Address::StackSlotAddress(source));
1773 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) { 1774 } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
1774 DRegister dst = EvenDRegisterOf(destination.fpu_reg()); 1775 DRegister dst = EvenDRegisterOf(destination.fpu_reg());
1775 DRegister src = EvenDRegisterOf(source.fpu_reg()); 1776 DRegister src = EvenDRegisterOf(source.fpu_reg());
1776 __ vmovd(DTMP, src); 1777 __ vmovd(DTMP, src);
1777 __ vmovd(src, dst); 1778 __ vmovd(src, dst);
1778 __ vmovd(dst, DTMP); 1779 __ vmovd(dst, DTMP);
1779 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) { 1780 } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
1780 ASSERT(destination.IsDoubleStackSlot() || 1781 ASSERT(destination.IsDoubleStackSlot() ||
1781 destination.IsQuadStackSlot() || 1782 destination.IsQuadStackSlot() ||
1782 source.IsDoubleStackSlot() || 1783 source.IsDoubleStackSlot() ||
1783 source.IsQuadStackSlot()); 1784 source.IsQuadStackSlot());
1784 bool double_width = destination.IsDoubleStackSlot() || 1785 bool double_width = destination.IsDoubleStackSlot() ||
1785 source.IsDoubleStackSlot(); 1786 source.IsDoubleStackSlot();
1786 QRegister qreg = source.IsFpuRegister() ? source.fpu_reg() 1787 QRegister qreg = source.IsFpuRegister() ? source.fpu_reg()
1787 : destination.fpu_reg(); 1788 : destination.fpu_reg();
1788 DRegister reg = EvenDRegisterOf(qreg); 1789 DRegister reg = EvenDRegisterOf(qreg);
1789 const Address& slot_address = source.IsFpuRegister() 1790 const Address& slot_address = source.IsFpuRegister()
1790 ? destination.ToStackSlotAddress() 1791 ? Address::StackSlotAddress(destination)
1791 : source.ToStackSlotAddress(); 1792 : Address::StackSlotAddress(source);
1792 1793
1793 if (double_width) { 1794 if (double_width) {
1794 __ vldrd(DTMP, slot_address); 1795 __ vldrd(DTMP, slot_address);
1795 __ vstrd(reg, slot_address); 1796 __ vstrd(reg, slot_address);
1796 __ vmovd(reg, DTMP); 1797 __ vmovd(reg, DTMP);
1797 } else { 1798 } else {
1798 UNIMPLEMENTED(); 1799 UNIMPLEMENTED();
1799 } 1800 }
1800 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) { 1801 } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
1801 const Address& source_slot_address = source.ToStackSlotAddress(); 1802 const Address& source_slot_address = Address::StackSlotAddress(source);
1802 const Address& destination_slot_address = destination.ToStackSlotAddress(); 1803 const Address& destination_slot_address =
1804 Address::StackSlotAddress(destination);
1803 1805
1804 ScratchFpuRegisterScope ensure_scratch(this, QTMP); 1806 ScratchFpuRegisterScope ensure_scratch(this, QTMP);
1805 DRegister scratch = EvenDRegisterOf(ensure_scratch.reg()); 1807 DRegister scratch = EvenDRegisterOf(ensure_scratch.reg());
1806 __ vldrd(DTMP, source_slot_address); 1808 __ vldrd(DTMP, source_slot_address);
1807 __ vldrd(scratch, destination_slot_address); 1809 __ vldrd(scratch, destination_slot_address);
1808 __ vstrd(DTMP, destination_slot_address); 1810 __ vstrd(DTMP, destination_slot_address);
1809 __ vstrd(scratch, source_slot_address); 1811 __ vstrd(scratch, source_slot_address);
1810 } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) { 1812 } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) {
1811 UNIMPLEMENTED(); 1813 UNIMPLEMENTED();
1812 } else { 1814 } else {
(...skipping 68 matching lines...) Expand 10 before | Expand all | Expand 10 after
1881 DRegister dreg = EvenDRegisterOf(reg); 1883 DRegister dreg = EvenDRegisterOf(reg);
1882 __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex)); 1884 __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex));
1883 } 1885 }
1884 1886
1885 1887
1886 #undef __ 1888 #undef __
1887 1889
1888 } // namespace dart 1890 } // namespace dart
1889 1891
1890 #endif // defined TARGET_ARCH_ARM 1892 #endif // defined TARGET_ARCH_ARM
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