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| 1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
| 2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
| 3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
| 4 // met: | 4 // met: |
| 5 // | 5 // |
| 6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
| 7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
| 8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
| 9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
| 10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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| 95 return ((value & ((1UL << rotate) - 1UL)) << (width - rotate)) | | 95 return ((value & ((1UL << rotate) - 1UL)) << (width - rotate)) | |
| 96 (value >> rotate); | 96 (value >> rotate); |
| 97 } | 97 } |
| 98 | 98 |
| 99 | 99 |
| 100 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, | 100 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, |
| 101 uint64_t value, | 101 uint64_t value, |
| 102 unsigned width) { | 102 unsigned width) { |
| 103 ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) || | 103 ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) || |
| 104 (width == 32)); | 104 (width == 32)); |
| 105 ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); | 105 ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); |
| 106 uint64_t result = value & ((1UL << width) - 1UL); | 106 uint64_t result = value & ((1UL << width) - 1UL); |
| 107 for (unsigned i = width; i < reg_size; i *= 2) { | 107 for (unsigned i = width; i < reg_size; i *= 2) { |
| 108 result |= (result << i); | 108 result |= (result << i); |
| 109 } | 109 } |
| 110 return result; | 110 return result; |
| 111 } | 111 } |
| 112 | 112 |
| 113 | 113 |
| 114 // Logical immediates can't encode zero, so a return value of zero is used to | 114 // Logical immediates can't encode zero, so a return value of zero is used to |
| 115 // indicate a failure case. Specifically, where the constraints on imm_s are not | 115 // indicate a failure case. Specifically, where the constraints on imm_s are not |
| 116 // met. | 116 // met. |
| 117 uint64_t Instruction::ImmLogical() { | 117 uint64_t Instruction::ImmLogical() { |
| 118 unsigned reg_size = SixtyFourBits() ? kXRegSize : kWRegSize; | 118 unsigned reg_size = SixtyFourBits() ? kXRegSizeInBits : kWRegSizeInBits; |
| 119 int64_t n = BitN(); | 119 int64_t n = BitN(); |
| 120 int64_t imm_s = ImmSetBits(); | 120 int64_t imm_s = ImmSetBits(); |
| 121 int64_t imm_r = ImmRotate(); | 121 int64_t imm_r = ImmRotate(); |
| 122 | 122 |
| 123 // An integer is constructed from the n, imm_s and imm_r bits according to | 123 // An integer is constructed from the n, imm_s and imm_r bits according to |
| 124 // the following table: | 124 // the following table: |
| 125 // | 125 // |
| 126 // N imms immr size S R | 126 // N imms immr size S R |
| 127 // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) | 127 // 1 ssssss rrrrrr 64 UInt(ssssss) UInt(rrrrrr) |
| 128 // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) | 128 // 0 0sssss xrrrrr 32 UInt(sssss) UInt(rrrrr) |
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| 325 uint64_t payload = ImmMoveWide(); | 325 uint64_t payload = ImmMoveWide(); |
| 326 // TODO(all): If we extend ::InlineData() to support bigger data, we need | 326 // TODO(all): If we extend ::InlineData() to support bigger data, we need |
| 327 // to update this method too. | 327 // to update this method too. |
| 328 return payload; | 328 return payload; |
| 329 } | 329 } |
| 330 | 330 |
| 331 | 331 |
| 332 } } // namespace v8::internal | 332 } } // namespace v8::internal |
| 333 | 333 |
| 334 #endif // V8_TARGET_ARCH_A64 | 334 #endif // V8_TARGET_ARCH_A64 |
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