A64: Rename k<Y>RegSize to k<Y>RegSizeInBits, and k<Y>RegSizeInBytes to k<Y>RegSize.

src/a64/disasm-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 237 matching lines @@
     Format(instr, "unallocated", "(LogicalImmediate)");
     return;
   }
 
   switch (instr->Mask(LogicalImmediateMask)) {
     case AND_w_imm:
     case AND_x_imm: mnemonic = "and"; break;
     case ORR_w_imm:
     case ORR_x_imm: {
       mnemonic = "orr";
-      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize
-                                                        : kWRegSize;
+      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
+                                                        : kWRegSizeInBits;
       if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) {
         mnemonic = "mov";
         form = "'Rds, 'ITri";
       }
       break;
     }
     case EOR_w_imm:
     case EOR_x_imm: mnemonic = "eor"; break;
     case ANDS_w_imm:
     case ANDS_x_imm: {
       mnemonic = "ands";
       if (rd_is_zr) {
         mnemonic = "tst";
         form = "'Rn, 'ITri";
       }
       break;
     }
     default: UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
 bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
-  ASSERT((reg_size == kXRegSize) ||
-         ((reg_size == kWRegSize) && (value <= 0xffffffff)));
+  ASSERT((reg_size == kXRegSizeInBits) ||
+         ((reg_size == kWRegSizeInBits) && (value <= 0xffffffff)));
 
   // Test for movz: 16-bits set at positions 0, 16, 32 or 48.
   if (((value & 0xffffffffffff0000UL) == 0UL) ||
       ((value & 0xffffffff0000ffffUL) == 0UL) ||
       ((value & 0xffff0000ffffffffUL) == 0UL) ||
       ((value & 0x0000ffffffffffffUL) == 0UL)) {
     return true;
   }
 
   // Test for movn: NOT(16-bits set at positions 0, 16, 32 or 48).
-  if ((reg_size == kXRegSize) &&
+  if ((reg_size == kXRegSizeInBits) &&
       (((value & 0xffffffffffff0000UL) == 0xffffffffffff0000UL) ||
        ((value & 0xffffffff0000ffffUL) == 0xffffffff0000ffffUL) ||
        ((value & 0xffff0000ffffffffUL) == 0xffff0000ffffffffUL) ||
        ((value & 0x0000ffffffffffffUL) == 0x0000ffffffffffffUL))) {
     return true;
   }
-  if ((reg_size == kWRegSize) &&
+  if ((reg_size == kWRegSizeInBits) &&
       (((value & 0xffff0000) == 0xffff0000) ||
        ((value & 0x0000ffff) == 0x0000ffff))) {
     return true;
   }
   return false;
 }
 
 
 void Disassembler::VisitLogicalShifted(Instruction* instr) {
   bool rd_is_zr = RdIsZROrSP(instr);
@@ skipping 126 matching lines @@
     default: UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
 void Disassembler::VisitBitfield(Instruction* instr) {
   unsigned s = instr->ImmS();
   unsigned r = instr->ImmR();
   unsigned rd_size_minus_1 =
-    ((instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize) - 1;
+    ((instr->SixtyFourBits() == 1) ? kXRegSizeInBits : kWRegSizeInBits) - 1;
   const char *mnemonic = "";
   const char *form = "";
   const char *form_shift_right = "'Rd, 'Rn, 'IBr";
   const char *form_extend = "'Rd, 'Wn";
   const char *form_bfiz = "'Rd, 'Rn, 'IBZ-r, 'IBs+1";
   const char *form_bfx = "'Rd, 'Rn, 'IBr, 'IBs-r+1";
   const char *form_lsl = "'Rd, 'Rn, 'IBZ-r";
 
   switch (instr->Mask(BitfieldMask)) {
     case SBFM_w:
@@ skipping 1050 matching lines @@
         AppendToOutput("#%d", s + 1);
         return 5;
       } else {
         ASSERT(format[3] == '-');
         AppendToOutput("#%d", s - r + 1);
         return 7;
       }
     }
     case 'Z': {  // IBZ-r.
       ASSERT((format[3] == '-') && (format[4] == 'r'));
-      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize;
+      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
+                                                        : kWRegSizeInBits;
       AppendToOutput("#%d", reg_size - r);
       return 5;
     }
     default: {
       UNREACHABLE();
       return 0;
     }
   }
 }
 
@@ skipping 314 matching lines @@
   decoder.AppendVisitor(&disasm);
 
   for (byte* pc = start; pc < end; pc += v8::internal::kInstructionSize) {
     decoder.Decode(reinterpret_cast<v8::internal::Instruction*>(pc));
   }
 }
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_A64