A64: Rename k<Y>RegSize to k<Y>RegSizeInBits, and k<Y>RegSizeInBytes to k<Y>RegSize.

src/a64/assembler-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
@@ skipping 102 matching lines @@
 }
 
 
 // This function defines the list of registers which are associated with a
 // safepoint slot. Safepoint register slots are saved contiguously on the stack.
 // MacroAssembler::SafepointRegisterStackIndex handles mapping from register
 // code to index in the safepoint register slots. Any change here can affect
 // this mapping.
 CPURegList CPURegList::GetSafepointSavedRegisters() {
   CPURegList list = CPURegList::GetCalleeSaved();
-  list.Combine(CPURegList(CPURegister::kRegister, kXRegSize, kJSCallerSaved));
+  list.Combine(
+      CPURegList(CPURegister::kRegister, kXRegSizeInBits, kJSCallerSaved));
 
   // Note that unfortunately we can't use symbolic names for registers and have
   // to directly use register codes. This is because this function is used to
   // initialize some static variables and we can't rely on register variables
   // to be initialized due to static initialization order issues in C++.
 
   // Drop ip0 and ip1 (i.e. x16 and x17), as they should not be expected to be
   // preserved outside of the macro assembler.
   list.Remove(16);
   list.Remove(17);
@@ skipping 607 matching lines @@
                      Label* label) {
   positions_recorder()->WriteRecordedPositions();
   cbnz(rt, LinkAndGetInstructionOffsetTo(label));
 }
 
 
 void Assembler::tbz(const Register& rt,
                     unsigned bit_pos,
                     int imm14) {
   positions_recorder()->WriteRecordedPositions();
-  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize)));
+  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
   Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
 }
 
 
 void Assembler::tbz(const Register& rt,
                     unsigned bit_pos,
                     Label* label) {
   positions_recorder()->WriteRecordedPositions();
   tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
 }
 
 
 void Assembler::tbnz(const Register& rt,
                      unsigned bit_pos,
                      int imm14) {
   positions_recorder()->WriteRecordedPositions();
-  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize)));
+  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
   Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
 }
 
 
 void Assembler::tbnz(const Register& rt,
                      unsigned bit_pos,
                      Label* label) {
   positions_recorder()->WriteRecordedPositions();
   tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
 }
@@ skipping 1299 matching lines @@
   if ((non_shift_bits > high_bit) || (non_shift_bits == 0)) {
     switch (extend) {
       case UXTB:
       case UXTH:
       case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break;
       case SXTB:
       case SXTH:
       case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break;
       case UXTX:
       case SXTX: {
-        ASSERT(rn.SizeInBits() == kXRegSize);
+        ASSERT(rn.SizeInBits() == kXRegSizeInBits);
         // Nothing to extend. Just shift.
         lsl(rd, rn_, left_shift);
         break;
       }
       default: UNREACHABLE();
     }
   } else {
     // No need to extend as the extended bits would be shifted away.
     lsl(rd, rn_, left_shift);
   }
@@ skipping 124 matching lines @@
 // imm_s and imm_r are updated with immediates encoded in the format required
 // by the corresponding fields in the logical instruction.
 // If it can not be encoded, the function returns false, and the values pointed
 // to by n, imm_s and imm_r are undefined.
 bool Assembler::IsImmLogical(uint64_t value,
                              unsigned width,
                              unsigned* n,
                              unsigned* imm_s,
                              unsigned* imm_r) {
   ASSERT((n != NULL) && (imm_s != NULL) && (imm_r != NULL));
-  ASSERT((width == kWRegSize) || (width == kXRegSize));
+  ASSERT((width == kWRegSizeInBits) || (width == kXRegSizeInBits));
 
   // Logical immediates are encoded using parameters n, imm_s and imm_r using
   // the following table:
   //
   //  N   imms    immr    size        S             R
   //  1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
   //  0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
   //  0  10ssss  xxrrrr    16    UInt(ssss)    UInt(rrrr)
   //  0  110sss  xxxrrr     8    UInt(sss)     UInt(rrr)
   //  0  1110ss  xxxxrr     4    UInt(ss)      UInt(rr)
   //  0  11110s  xxxxxr     2    UInt(s)       UInt(r)
   // (s bits must not be all set)
   //
   // A pattern is constructed of size bits, where the least significant S+1
   // bits are set. The pattern is rotated right by R, and repeated across a
   // 32 or 64-bit value, depending on destination register width.
   //
   // To test if an arbitary immediate can be encoded using this scheme, an
   // iterative algorithm is used.
   //
   // TODO(mcapewel) This code does not consider using X/W register overlap to
   // support 64-bit immediates where the top 32-bits are zero, and the bottom
   // 32-bits are an encodable logical immediate.
 
   // 1. If the value has all set or all clear bits, it can't be encoded.
   if ((value == 0) || (value == 0xffffffffffffffffUL) ||
-      ((width == kWRegSize) && (value == 0xffffffff))) {
+      ((width == kWRegSizeInBits) && (value == 0xffffffff))) {
     return false;
   }
 
   unsigned lead_zero = CountLeadingZeros(value, width);
   unsigned lead_one = CountLeadingZeros(~value, width);
   unsigned trail_zero = CountTrailingZeros(value, width);
   unsigned trail_one = CountTrailingZeros(~value, width);
   unsigned set_bits = CountSetBits(value, width);
 
   // The fixed bits in the immediate s field.
   // If width == 64 (X reg), start at 0xFFFFFF80.
   // If width == 32 (W reg), start at 0xFFFFFFC0, as the iteration for 64-bit
   // widths won't be executed.
-  int imm_s_fixed = (width == kXRegSize) ? -128 : -64;
+  int imm_s_fixed = (width == kXRegSizeInBits) ? -128 : -64;
   int imm_s_mask = 0x3F;
 
   for (;;) {
     // 2. If the value is two bits wide, it can be encoded.
     if (width == 2) {
       *n = 0;
       *imm_s = 0x3C;
       *imm_r = (value & 3) - 1;
       return true;
     }
@@ skipping 454 matching lines @@
   // code.
 #ifdef ENABLE_DEBUGGER_SUPPORT
   RecordRelocInfo(RelocInfo::CONST_POOL, static_cast<intptr_t>(size));
 #endif
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64