A64: Rename k<Y>RegSize to k<Y>RegSizeInBits, and k<Y>RegSizeInBytes to k<Y>RegSize.

src/a64/assembler-a64-inl.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 91 matching lines @@
     return true;
   } else {
     ASSERT(IsNone());
     return false;
   }
 }
 
 
 inline bool CPURegister::IsValidRegister() const {
   return IsRegister() &&
-         ((reg_size == kWRegSize) || (reg_size == kXRegSize)) &&
+         ((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)) &&
          ((reg_code < kNumberOfRegisters) || (reg_code == kSPRegInternalCode));
 }
 
 
 inline bool CPURegister::IsValidFPRegister() const {
   return IsFPRegister() &&
-         ((reg_size == kSRegSize) || (reg_size == kDRegSize)) &&
+         ((reg_size == kSRegSizeInBits) || (reg_size == kDRegSizeInBits)) &&
          (reg_code < kNumberOfFPRegisters);
 }
 
 
 inline bool CPURegister::IsNone() const {
   // kNoRegister types should always have size 0 and code 0.
   ASSERT((reg_type != kNoRegister) || (reg_code == 0));
   ASSERT((reg_type != kNoRegister) || (reg_size == 0));
 
   return reg_type == kNoRegister;
@@ skipping 84 matching lines @@
   ASSERT(IsValid());
   ASSERT(CPURegister::Create(code, size_, type_).IsValid());
   list_ &= ~(1UL << code);
 }
 
 
 inline Register Register::XRegFromCode(unsigned code) {
   // This function returns the zero register when code = 31. The stack pointer
   // can not be returned.
   ASSERT(code < kNumberOfRegisters);
-  return Register::Create(code, kXRegSize);
+  return Register::Create(code, kXRegSizeInBits);
 }
 
 
 inline Register Register::WRegFromCode(unsigned code) {
   ASSERT(code < kNumberOfRegisters);
-  return Register::Create(code, kWRegSize);
+  return Register::Create(code, kWRegSizeInBits);
 }
 
 
 inline FPRegister FPRegister::SRegFromCode(unsigned code) {
   ASSERT(code < kNumberOfFPRegisters);
-  return FPRegister::Create(code, kSRegSize);
+  return FPRegister::Create(code, kSRegSizeInBits);
 }
 
 
 inline FPRegister FPRegister::DRegFromCode(unsigned code) {
   ASSERT(code < kNumberOfFPRegisters);
-  return FPRegister::Create(code, kDRegSize);
+  return FPRegister::Create(code, kDRegSizeInBits);
 }
 
 
 inline Register CPURegister::W() const {
   ASSERT(IsValidRegister());
   return Register::WRegFromCode(reg_code);
 }
 
 
 inline Register CPURegister::X() const {
@@ skipping 74 matching lines @@
   STATIC_ASSERT(OperandInitializer<T>::kIsIntType);
 }
 
 
 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
     : reg_(reg),
       shift_(shift),
       extend_(NO_EXTEND),
       shift_amount_(shift_amount),
       rmode_(reg.Is64Bits() ? RelocInfo::NONE64 : RelocInfo::NONE32) {
-  ASSERT(reg.Is64Bits() || (shift_amount < kWRegSize));
-  ASSERT(reg.Is32Bits() || (shift_amount < kXRegSize));
+  ASSERT(reg.Is64Bits() || (shift_amount < kWRegSizeInBits));
+  ASSERT(reg.Is32Bits() || (shift_amount < kXRegSizeInBits));
   ASSERT(!reg.IsSP());
 }
 
 
 Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
     : reg_(reg),
       shift_(NO_SHIFT),
       extend_(extend),
       shift_amount_(shift_amount),
       rmode_(reg.Is64Bits() ? RelocInfo::NONE64 : RelocInfo::NONE32) {
@@ skipping 650 matching lines @@
   ASSERT(IsImmAddSub(imm));
   if (is_uint12(imm)) {  // No shift required.
     return imm << ImmAddSub_offset;
   } else {
     return ((imm >> 12) << ImmAddSub_offset) | (1 << ShiftAddSub_offset);
   }
 }
 
 
 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
-  ASSERT(((reg_size == kXRegSize) && is_uint6(imms)) ||
-         ((reg_size == kWRegSize) && is_uint5(imms)));
+  ASSERT(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
+         ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
   USE(reg_size);
   return imms << ImmS_offset;
 }
 
 
 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
-  ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) ||
-         ((reg_size == kWRegSize) && is_uint5(immr)));
+  ASSERT(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
+         ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
   USE(reg_size);
   ASSERT(is_uint6(immr));
   return immr << ImmR_offset;
 }
 
 
 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
-  ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
+  ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
   ASSERT(is_uint6(imms));
-  ASSERT((reg_size == kXRegSize) || is_uint6(imms + 3));
+  ASSERT((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
   USE(reg_size);
   return imms << ImmSetBits_offset;
 }
 
 
 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) {
-  ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
-  ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) ||
-         ((reg_size == kWRegSize) && is_uint5(immr)));
+  ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
+  ASSERT(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
+         ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
   USE(reg_size);
   return immr << ImmRotate_offset;
 }
 
 
 Instr Assembler::ImmLLiteral(int imm19) {
   CHECK(is_int19(imm19));
   return truncate_to_int19(imm19) << ImmLLiteral_offset;
 }
 
 
 Instr Assembler::BitN(unsigned bitn, unsigned reg_size) {
-  ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
-  ASSERT((reg_size == kXRegSize) || (bitn == 0));
+  ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
+  ASSERT((reg_size == kXRegSizeInBits) || (bitn == 0));
   USE(reg_size);
   return bitn << BitN_offset;
 }
 
 
 Instr Assembler::ShiftDP(Shift shift) {
   ASSERT(shift == LSL || shift == LSR || shift == ASR || shift == ROR);
   return shift << ShiftDP_offset;
 }
 
@@ skipping 142 matching lines @@
 
 
 void Assembler::ClearRecordedAstId() {
   recorded_ast_id_ = TypeFeedbackId::None();
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_A64_ASSEMBLER_A64_INL_H_