Adds the vtbl ARM SIMD instruction.

runtime/vm/assembler_arm.cc

Index: runtime/vm/assembler_arm.cc
===================================================================
--- runtime/vm/assembler_arm.cc	(revision 25066)
+++ runtime/vm/assembler_arm.cc	(working copy)
@@ -1219,33 +1219,35 @@
 }
 
 
-void Assembler::EmitSIMDqqq(int32_t opcode, OperandSize size,
-                            QRegister qd, QRegister qn, QRegister qm) {
-  int sz = 0;
+static inline int ShiftOfOperandSize(OperandSize size) {
   switch (size) {
     case kByte:
     case kUnsignedByte:
-      sz = 0;
-      break;
+      return 0;
     case kHalfword:
     case kUnsignedHalfword:
-      sz = 1;
-      break;
+      return 1;
     case kWord:
     case kUnsignedWord:
-      sz = 2;
-      break;
+      return 2;
     case kWordPair:
-      sz = 3;
-      break;
+      return 3;
     case kSWord:
     case kDWord:
-      sz = 0;
-      break;
+      return 0;
     default:
       UNREACHABLE();
       break;
   }
+
+  UNREACHABLE();
+  return -1;
+}
+
+
+void Assembler::EmitSIMDqqq(int32_t opcode, OperandSize size,
+                            QRegister qd, QRegister qn, QRegister qm) {
+  int sz = ShiftOfOperandSize(size);
   int32_t encoding =
       (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
       B25 | B6 |
@@ -1260,6 +1262,23 @@
 }
 
 
+void Assembler::EmitSIMDddd(int32_t opcode, OperandSize size,
+                            DRegister dd, DRegister dn, DRegister dm) {
+  int sz = ShiftOfOperandSize(size);
+  int32_t encoding =
+      (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
+      B25 |
+      opcode | ((sz & 0x3) * B20) |
+      ((static_cast<int32_t>(dd) >> 4)*B22) |
+      ((static_cast<int32_t>(dn) & 0xf)*B16) |
+      ((static_cast<int32_t>(dd) & 0xf)*B12) |
+      ((static_cast<int32_t>(dn) >> 4)*B7) |
+      ((static_cast<int32_t>(dm) >> 4)*B5) |
+      (static_cast<int32_t>(dm) & 0xf);
+  Emit(encoding);
+}
+
+
 void Assembler::vaddqi(OperandSize sz,
                        QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11, sz, qd, qn, qm);
@@ -1293,6 +1312,12 @@
 }
 
 
+void Assembler::vtbl(DRegister dd, DRegister dn, int len, DRegister dm) {
+  ASSERT((len >= 1) && (len <= 4));
+  EmitSIMDddd(B24 | B23 | B11 | ((len - 1) * B8), kWordPair, dd, dn, dm);
+}
+
+
 void Assembler::svc(uint32_t imm24, Condition cond) {
   ASSERT(cond != kNoCondition);
   ASSERT(imm24 < (1 << 24));