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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include <math.h> // for isnan. | 5 #include <math.h> // for isnan. |
| 6 #include <setjmp.h> | 6 #include <setjmp.h> |
| 7 #include <stdlib.h> | 7 #include <stdlib.h> |
| 8 | 8 |
| 9 #include "vm/globals.h" | 9 #include "vm/globals.h" |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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| 3007 for (int i = 0; i < 4; i++) { | 3007 for (int i = 0; i < 4; i++) { |
| 3008 s8d.data_[i].f = s8n.data_[i].f * s8m.data_[i].f; | 3008 s8d.data_[i].f = s8n.data_[i].f * s8m.data_[i].f; |
| 3009 } | 3009 } |
| 3010 } else { | 3010 } else { |
| 3011 UnimplementedInstruction(instr); | 3011 UnimplementedInstruction(instr); |
| 3012 } | 3012 } |
| 3013 | 3013 |
| 3014 set_qregister(qd, s8d); | 3014 set_qregister(qd, s8d); |
| 3015 } else { | 3015 } else { |
| 3016 // Q == 0, Uses 64-bit D registers. | 3016 // Q == 0, Uses 64-bit D registers. |
| 3017 UnimplementedInstruction(instr); | 3017 if ((instr->Bits(23, 2) == 3) && (instr->Bits(20, 2) == 3) && |
| 3018 (instr->Bits(10, 2) == 2) && (instr->Bit(4) == 0)) { |
| 3019 // Format(instr, "vtbl 'dd, 'dtbllist, 'dm"); |
| 3020 DRegister dd = instr->DdField(); |
| 3021 DRegister dm = instr->DmField(); |
| 3022 int reg_count = instr->Bits(8, 2) + 1; |
| 3023 int start = (instr->Bit(7) << 4) | instr->Bits(16, 4); |
| 3024 int64_t table[4]; |
| 3025 |
| 3026 for (int i = 0; i < reg_count; i++) { |
| 3027 DRegister d = static_cast<DRegister>(start + i); |
| 3028 table[i] = get_dregister_bits(d); |
| 3029 } |
| 3030 for (int i = reg_count; i < 4; i++) { |
| 3031 table[i] = 0; |
| 3032 } |
| 3033 |
| 3034 |
| 3035 int64_t dm_value = get_dregister_bits(dm); |
| 3036 int64_t result; |
| 3037 int8_t* dm_bytes = reinterpret_cast<int8_t*>(&dm_value); |
| 3038 int8_t* result_bytes = reinterpret_cast<int8_t*>(&result); |
| 3039 int8_t* table_bytes = reinterpret_cast<int8_t*>(&table[0]); |
| 3040 for (int i = 0; i < 8; i++) { |
| 3041 int idx = dm_bytes[i]; |
| 3042 if ((idx >= 0) && (idx < 256)) { |
| 3043 result_bytes[i] = table_bytes[idx]; |
| 3044 } else { |
| 3045 result_bytes[i] = 0; |
| 3046 } |
| 3047 } |
| 3048 |
| 3049 set_dregister_bits(dd, result); |
| 3050 } else { |
| 3051 UnimplementedInstruction(instr); |
| 3052 } |
| 3018 } | 3053 } |
| 3019 } | 3054 } |
| 3020 | 3055 |
| 3021 | 3056 |
| 3022 // Executes the current instruction. | 3057 // Executes the current instruction. |
| 3023 void Simulator::InstructionDecode(Instr* instr) { | 3058 void Simulator::InstructionDecode(Instr* instr) { |
| 3024 pc_modified_ = false; | 3059 pc_modified_ = false; |
| 3025 if (FLAG_trace_sim) { | 3060 if (FLAG_trace_sim) { |
| 3026 const uword start = reinterpret_cast<uword>(instr); | 3061 const uword start = reinterpret_cast<uword>(instr); |
| 3027 const uword end = start + Instr::kInstrSize; | 3062 const uword end = start + Instr::kInstrSize; |
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| 3253 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); | 3288 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); |
| 3254 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); | 3289 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); |
| 3255 buf->Longjmp(); | 3290 buf->Longjmp(); |
| 3256 } | 3291 } |
| 3257 | 3292 |
| 3258 } // namespace dart | 3293 } // namespace dart |
| 3259 | 3294 |
| 3260 #endif // !defined(HOST_ARCH_ARM) | 3295 #endif // !defined(HOST_ARCH_ARM) |
| 3261 | 3296 |
| 3262 #endif // defined TARGET_ARCH_ARM | 3297 #endif // defined TARGET_ARCH_ARM |
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