Adds the vtbl ARM SIMD instruction.

runtime/vm/disassembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 #include "platform/assert.h"
 
@@ skipping 15 matching lines @@
   void InstructionDecode(uword pc);
 
  private:
   // Bottleneck functions to print into the out_buffer.
   void Print(const char* str);
 
   // Printing of common values.
   void PrintRegister(int reg);
   void PrintSRegister(int reg);
   void PrintDRegister(int reg);
+  void PrintDRegisterList(int start, int reg_count);
   void PrintQRegister(int reg);
   void PrintCondition(Instr* instr);
   void PrintShiftRm(Instr* instr);
   void PrintShiftImm(Instr* instr);
   void PrintPU(Instr* instr);
 
   // Handle formatting of instructions and their options.
   int FormatRegister(Instr* instr, const char* option);
   int FormatSRegister(Instr* instr, const char* option);
   int FormatDRegister(Instr* instr, const char* option);
@@ skipping 277 matching lines @@
       }
     }
     Print("}");
     return 5;
   }
   UNREACHABLE();
   return -1;
 }
 
 
+void ARMDecoder::PrintDRegisterList(int start, int reg_count) {
+  Print("{");
+  for (int i = start; i < start + reg_count; i++) {
+    PrintDRegister(i);
+    if (i != start + reg_count - 1) {
+      Print(", ");
+    }
+  }
+  Print("}");
+}
+
+
 int ARMDecoder::FormatDRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'd');
   if (format[1] == 'n') {  // 'dn: Dn register
     int reg = instr->DnField();
     PrintDRegister(reg);
     return 2;
   } else if (format[1] == 'd') {  // 'dd: Dd register
     int reg = instr->DdField();
     PrintDRegister(reg);
     return 2;
   } else if (format[1] == 'm') {  // 'dm: Dm register
     int reg = instr->DmField();
     PrintDRegister(reg);
     return 2;
   } else if (format[1] == 'l') {
     ASSERT(STRING_STARTS_WITH(format, "dlist"));
     int reg_count = instr->Bits(0, 8) >> 1;
     int start = (instr->Bit(22) << 4) | instr->Bits(12, 4);
-    Print("{");
-    for (int i = start; i < start + reg_count; i++) {
-      PrintDRegister(i);
-      if (i != start + reg_count - 1) {
-        Print(", ");
-      }
-    }
-    Print("}");
+    PrintDRegisterList(start, reg_count);
     return 5;
+  } else if (format[1] == 't') {
+    ASSERT(STRING_STARTS_WITH(format, "dtbllist"));
+    int reg_count = instr->Bits(8, 2) + 1;
+    int start = (instr->Bit(7) << 4) | instr->Bits(16, 4);
+    PrintDRegisterList(start, reg_count);
+    return 8;
   }
   UNREACHABLE();
   return -1;
 }
 
 
 int ARMDecoder::FormatQRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'q');
   if (format[1] == 'n') {  // 'qn: Qn register
     int reg = instr->QnField();
@@ skipping 922 matching lines @@
     } else if ((instr->Bits(8, 4) == 9) && (instr->Bit(4) == 1) &&
                (instr->Bits(23, 2) == 0)) {
       Format(instr, "vmulq'sz 'qd, 'qn, 'qm");
     } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 1) &&
                (instr->Bits(23, 2) == 2) && (instr->Bit(21) == 0)) {
       Format(instr, "vmulqs 'qd, 'qn, 'qm");
     } else {
       Unknown(instr);
     }
   } else {
-    Unknown(instr);
+    if ((instr->Bits(23, 2) == 3) && (instr->Bits(20, 2) == 3) &&
+        (instr->Bits(10, 2) == 2) && (instr->Bit(4) == 0)) {
+      Format(instr, "vtbl 'dd, 'dtbllist, 'dm");
+    } else {
+      Unknown(instr);
+    }
   }
 }
 
 
 void ARMDecoder::InstructionDecode(uword pc) {
   Instr* instr = Instr::At(pc);
 
   if (instr->ConditionField() == kSpecialCondition) {
     if (instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) {
       Format(instr, "clrex");
@@ skipping 86 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM