Adds the vtbl ARM SIMD instruction.

runtime/vm/assembler_arm_test.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/os.h"
 #include "vm/unit_test.h"
@@ skipping 2143 matching lines @@
 }
 
 
 ASSEMBLER_TEST_RUN(Vmulqs, test) {
   EXPECT(test != NULL);
   typedef int (*Tst)();
   EXPECT_EQ(70, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
 }
 
 
+ASSEMBLER_TEST_GENERATE(VtblX, assembler) {

[regis, 2013/07/16 20:57:14]

The name VtblX is somewhat confusing, because there is a variant of the vtbl
instruction called vtblx, but this test has nothing to do with it.
It becomes clear when you see the name of the following tests. Feel free to
ignore.

[zra, 2013/07/16 21:17:53]

I don't think we'll need the vtblx instruction, so I'll leave this as-is.

+  if (CPUFeatures::neon_supported()) {
+    // Index.
+    __ LoadImmediate(R0, 0x03020100);
+    __ vmovsr(S0, R0);
+    __ vmovsr(S1, R0);
+
+    // Table.
+    __ LoadSImmediate(S2, 1.0);
+    __ LoadSImmediate(S3, 2.0);
+    __ LoadSImmediate(S4, 3.0);
+    __ LoadSImmediate(S5, 4.0);
+
+    // Select.
+    __ vtbl(D3, D1, 2, D0);
+
+    // Check that S6, S7 are both 1.0
+    __ vcvtis(S0, S6);
+    __ vcvtis(S1, S7);
+    __ vmovrs(R2, S0);
+    __ vmovrs(R3, S1);
+
+    __ LoadImmediate(R0, 0);
+    __ CompareImmediate(R2, 1);
+    __ bx(LR, NE);
+    __ CompareImmediate(R3, 1);
+    __ bx(LR, NE);
+    __ LoadImmediate(R0, 42);
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, 42);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(VtblX, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(VtblY, assembler) {
+  if (CPUFeatures::neon_supported()) {
+    // Index.
+    __ LoadImmediate(R0, 0x07060504);
+    __ vmovsr(S0, R0);
+    __ vmovsr(S1, R0);
+
+    // Table.
+    __ LoadSImmediate(S2, 2.0);
+    __ LoadSImmediate(S3, 1.0);
+    __ LoadSImmediate(S4, 3.0);
+    __ LoadSImmediate(S5, 4.0);
+
+    // Select.
+    __ vtbl(D3, D1, 2, D0);
+
+    // Check that S6, S7 are both 1.0
+    __ vcvtis(S0, S6);
+    __ vcvtis(S1, S7);
+    __ vmovrs(R2, S0);
+    __ vmovrs(R3, S1);
+
+    __ LoadImmediate(R0, 0);
+    __ CompareImmediate(R2, 1);
+    __ bx(LR, NE);
+    __ CompareImmediate(R3, 1);
+    __ bx(LR, NE);
+    __ LoadImmediate(R0, 42);
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, 42);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(VtblY, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(VtblZ, assembler) {
+  if (CPUFeatures::neon_supported()) {
+    // Index.
+    __ LoadImmediate(R0, 0x0b0a0908);
+    __ vmovsr(S0, R0);
+    __ vmovsr(S1, R0);
+
+    // Table.
+    __ LoadSImmediate(S2, 2.0);
+    __ LoadSImmediate(S3, 3.0);
+    __ LoadSImmediate(S4, 1.0);
+    __ LoadSImmediate(S5, 4.0);
+
+    // Select.
+    __ vtbl(D3, D1, 2, D0);
+
+    // Check that S6, S7 are both 1.0
+    __ vcvtis(S0, S6);
+    __ vcvtis(S1, S7);
+    __ vmovrs(R2, S0);
+    __ vmovrs(R3, S1);
+
+    __ LoadImmediate(R0, 0);
+    __ CompareImmediate(R2, 1);
+    __ bx(LR, NE);
+    __ CompareImmediate(R3, 1);
+    __ bx(LR, NE);
+    __ LoadImmediate(R0, 42);
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, 42);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(VtblZ, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(VtblW, assembler) {
+  if (CPUFeatures::neon_supported()) {
+    // Index.
+    __ LoadImmediate(R0, 0x0f0e0d0c);
+    __ vmovsr(S0, R0);
+    __ vmovsr(S1, R0);
+
+    // Table.
+    __ LoadSImmediate(S2, 2.0);
+    __ LoadSImmediate(S3, 3.0);
+    __ LoadSImmediate(S4, 4.0);
+    __ LoadSImmediate(S5, 1.0);
+
+    // Select.
+    __ vtbl(D3, D1, 2, D0);
+
+    // Check that S6, S7 are both 1.0
+    __ vcvtis(S0, S6);
+    __ vcvtis(S1, S7);
+    __ vmovrs(R2, S0);
+    __ vmovrs(R3, S1);
+
+    __ LoadImmediate(R0, 0);
+    __ CompareImmediate(R2, 1);
+    __ bx(LR, NE);
+    __ CompareImmediate(R3, 1);
+    __ bx(LR, NE);
+    __ LoadImmediate(R0, 42);
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, 42);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(VtblW, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(42, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
 // Called from assembler_test.cc.
 // LR: return address.
 // R0: context.
 // R1: value.
 // R2: growable array.
 ASSEMBLER_TEST_GENERATE(StoreIntoObject, assembler) {
   __ PushList((1 << CTX) | (1 << LR));
   __ mov(CTX, ShifterOperand(R0));
   __ StoreIntoObject(R2,
                      FieldAddress(R2, GrowableObjectArray::data_offset()),
                      R1);
   __ PopList((1 << CTX) | (1 << LR));
   __ Ret();
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM