Adds the vtbl ARM SIMD instruction.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
@@ skipping 1201 matching lines @@
 void Assembler::vmstat(Condition cond) {  // VMRS APSR_nzcv, FPSCR
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
                      (static_cast<int32_t>(PC)*B12) |
                      B11 | B9 | B4;
   Emit(encoding);
 }
 
 
+static inline int ShiftOfOperandSize(OperandSize size) {
+  switch (size) {
+    case kByte:
+    case kUnsignedByte:
+      return 0;
+    case kHalfword:
+    case kUnsignedHalfword:
+      return 1;
+    case kWord:
+    case kUnsignedWord:
+      return 2;
+    case kWordPair:
+      return 3;
+    case kSWord:
+    case kDWord:
+      return 0;
+    default:
+      UNREACHABLE();
+      break;
+  }
+
+  UNREACHABLE();
+  return -1;
+}
+
+
 void Assembler::EmitSIMDqqq(int32_t opcode, OperandSize size,
                             QRegister qd, QRegister qn, QRegister qm) {
-  int sz = 0;
-  switch (size) {
-    case kByte:
-    case kUnsignedByte:
-      sz = 0;
-      break;
-    case kHalfword:
-    case kUnsignedHalfword:
-      sz = 1;
-      break;
-    case kWord:
-    case kUnsignedWord:
-      sz = 2;
-      break;
-    case kWordPair:
-      sz = 3;
-      break;
-    case kSWord:
-    case kDWord:
-      sz = 0;
-      break;
-    default:
-      UNREACHABLE();
-      break;
-  }
+  int sz = ShiftOfOperandSize(size);
   int32_t encoding =
       (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
       B25 | B6 |
       opcode | ((sz & 0x3) * B20) |
       ((static_cast<int32_t>(qd * 2) >> 4)*B22) |
       ((static_cast<int32_t>(qn * 2) & 0xf)*B16) |
       ((static_cast<int32_t>(qd * 2) & 0xf)*B12) |
       ((static_cast<int32_t>(qn * 2) >> 4)*B7) |
       ((static_cast<int32_t>(qm * 2) >> 4)*B5) |
       (static_cast<int32_t>(qm * 2) & 0xf);
   Emit(encoding);
 }
 
 
+void Assembler::EmitSIMDddd(int32_t opcode, OperandSize size,
+                            DRegister dd, DRegister dn, DRegister dm) {
+  int sz = ShiftOfOperandSize(size);
+  int32_t encoding =
+      (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
+      B25 |
+      opcode | ((sz & 0x3) * B20) |
+      ((static_cast<int32_t>(dd) >> 4)*B22) |
+      ((static_cast<int32_t>(dn) & 0xf)*B16) |
+      ((static_cast<int32_t>(dd) & 0xf)*B12) |
+      ((static_cast<int32_t>(dn) >> 4)*B7) |
+      ((static_cast<int32_t>(dm) >> 4)*B5) |
+      (static_cast<int32_t>(dm) & 0xf);
+  Emit(encoding);
+}
+
+
 void Assembler::vaddqi(OperandSize sz,
                        QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11, sz, qd, qn, qm);
 }
 
 
 void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B8, kSWord, qd, qn, qm);
 }
 
@@ skipping 13 matching lines @@
                        QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B8 | B4, sz, qd, qn, qm);
 }
 
 
 void Assembler::vmulqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, kSWord, qd, qn, qm);
 }
 
 
+void Assembler::vtbl(DRegister dd, DRegister dn, int len, DRegister dm) {
+  ASSERT((len >= 1) && (len <= 4));
+  EmitSIMDddd(B24 | B23 | B11 | ((len - 1) * B8), kWordPair, dd, dn, dm);
+}
+
+
 void Assembler::svc(uint32_t imm24, Condition cond) {
   ASSERT(cond != kNoCondition);
   ASSERT(imm24 < (1 << 24));
   int32_t encoding = (cond << kConditionShift) | B27 | B26 | B25 | B24 | imm24;
   Emit(encoding);
 }
 
 
 void Assembler::bkpt(uint16_t imm16) {
   // bkpt requires that the cond field is AL.
@@ skipping 1042 matching lines @@
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM