| Index: src/compiler/x64/instruction-selector-x64.cc
|
| diff --git a/src/compiler/x64/instruction-selector-x64.cc b/src/compiler/x64/instruction-selector-x64.cc
|
| index b1af3e56d89e106ac159e6cc623643e771b99770..e494dd1d1f83db33c6f5a391f1353cd6d757b605 100644
|
| --- a/src/compiler/x64/instruction-selector-x64.cc
|
| +++ b/src/compiler/x64/instruction-selector-x64.cc
|
| @@ -2029,6 +2029,44 @@ void InstructionSelector::VisitAtomicLoad(Node* node) {
|
| VisitLoad(node);
|
| }
|
|
|
| +void InstructionSelector::VisitAtomicStore(Node* node) {
|
| + X64OperandGenerator g(this);
|
| + Node* base = node->InputAt(0);
|
| + Node* index = node->InputAt(1);
|
| + Node* value = node->InputAt(2);
|
| +
|
| + MachineRepresentation rep = AtomicStoreRepresentationOf(node->op());
|
| + ArchOpcode opcode = kArchNop;
|
| + switch (rep) {
|
| + case MachineRepresentation::kWord8:
|
| + opcode = kX64Xchgb;
|
| + break;
|
| + case MachineRepresentation::kWord16:
|
| + opcode = kX64Xchgw;
|
| + break;
|
| + case MachineRepresentation::kWord32:
|
| + opcode = kX64Xchgl;
|
| + break;
|
| + default:
|
| + UNREACHABLE();
|
| + return;
|
| + }
|
| + AddressingMode addressing_mode;
|
| + InstructionOperand inputs[4];
|
| + size_t input_count = 0;
|
| + inputs[input_count++] = g.UseUniqueRegister(base);
|
| + if (g.CanBeImmediate(index)) {
|
| + inputs[input_count++] = g.UseImmediate(index);
|
| + addressing_mode = kMode_MRI;
|
| + } else {
|
| + inputs[input_count++] = g.UseUniqueRegister(index);
|
| + addressing_mode = kMode_MR1;
|
| + }
|
| + inputs[input_count++] = g.UseUniqueRegister(value);
|
| + InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
|
| + Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count, inputs);
|
| +}
|
| +
|
| // static
|
| MachineOperatorBuilder::Flags
|
| InstructionSelector::SupportedMachineOperatorFlags() {
|
|
|