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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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357 Opcode opcode = Instruction::S390OpcodeValue(buffer_ + pos); | 357 Opcode opcode = Instruction::S390OpcodeValue(buffer_ + pos); |
358 | 358 |
359 if (is_branch != nullptr) { | 359 if (is_branch != nullptr) { |
360 *is_branch = (opcode == BRC || opcode == BRCT || opcode == BRCTG || | 360 *is_branch = (opcode == BRC || opcode == BRCT || opcode == BRCTG || |
361 opcode == BRCL || opcode == BRASL); | 361 opcode == BRCL || opcode == BRASL); |
362 } | 362 } |
363 | 363 |
364 if (BRC == opcode || BRCT == opcode || BRCTG == opcode) { | 364 if (BRC == opcode || BRCT == opcode || BRCTG == opcode) { |
365 int16_t imm16 = target_pos - pos; | 365 int16_t imm16 = target_pos - pos; |
366 instr &= (~0xffff); | 366 instr &= (~0xffff); |
367 CHECK(is_int16(imm16)); | 367 DCHECK(is_int16(imm16)); |
368 instr_at_put<FourByteInstr>(pos, instr | (imm16 >> 1)); | 368 instr_at_put<FourByteInstr>(pos, instr | (imm16 >> 1)); |
369 return; | 369 return; |
370 } else if (BRCL == opcode || LARL == opcode || BRASL == opcode) { | 370 } else if (BRCL == opcode || LARL == opcode || BRASL == opcode) { |
371 // Immediate is in # of halfwords | 371 // Immediate is in # of halfwords |
372 int32_t imm32 = target_pos - pos; | 372 int32_t imm32 = target_pos - pos; |
373 instr &= (~static_cast<uint64_t>(0xffffffff)); | 373 instr &= (~static_cast<uint64_t>(0xffffffff)); |
374 instr_at_put<SixByteInstr>(pos, instr | (imm32 >> 1)); | 374 instr_at_put<SixByteInstr>(pos, instr | (imm32 >> 1)); |
375 return; | 375 return; |
376 } else if (LLILF == opcode) { | 376 } else if (LLILF == opcode) { |
377 CHECK(target_pos == kEndOfChain || target_pos >= 0); | 377 DCHECK(target_pos == kEndOfChain || target_pos >= 0); |
378 // Emitted label constant, not part of a branch. | 378 // Emitted label constant, not part of a branch. |
379 // Make label relative to Code* of generated Code object. | 379 // Make label relative to Code* of generated Code object. |
380 int32_t imm32 = target_pos + (Code::kHeaderSize - kHeapObjectTag); | 380 int32_t imm32 = target_pos + (Code::kHeaderSize - kHeapObjectTag); |
381 instr &= (~static_cast<uint64_t>(0xffffffff)); | 381 instr &= (~static_cast<uint64_t>(0xffffffff)); |
382 instr_at_put<SixByteInstr>(pos, instr | imm32); | 382 instr_at_put<SixByteInstr>(pos, instr | imm32); |
383 return; | 383 return; |
384 } | 384 } |
385 DCHECK(false); | 385 DCHECK(false); |
386 } | 386 } |
387 | 387 |
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2531 sil_form(MVHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); | 2531 sil_form(MVHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); |
2532 } | 2532 } |
2533 | 2533 |
2534 // Move integer (64) | 2534 // Move integer (64) |
2535 void Assembler::mvghi(const MemOperand& opnd1, const Operand& i2) { | 2535 void Assembler::mvghi(const MemOperand& opnd1, const Operand& i2) { |
2536 sil_form(MVGHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); | 2536 sil_form(MVGHI, opnd1.getBaseRegister(), opnd1.getDisplacement(), i2); |
2537 } | 2537 } |
2538 | 2538 |
2539 // Store Register (64) | 2539 // Store Register (64) |
2540 void Assembler::stg(Register src, const MemOperand& dst) { | 2540 void Assembler::stg(Register src, const MemOperand& dst) { |
| 2541 DCHECK(!(dst.rb().code() == 15 && dst.offset() < 0)); |
2541 rxy_form(STG, src, dst.rx(), dst.rb(), dst.offset()); | 2542 rxy_form(STG, src, dst.rx(), dst.rb(), dst.offset()); |
2542 } | 2543 } |
2543 | 2544 |
2544 // Insert Character | 2545 // Insert Character |
2545 void Assembler::ic_z(Register r1, const MemOperand& opnd) { | 2546 void Assembler::ic_z(Register r1, const MemOperand& opnd) { |
2546 rx_form(IC_z, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2547 rx_form(IC_z, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2547 } | 2548 } |
2548 | 2549 |
2549 // Insert Character | 2550 // Insert Character |
2550 void Assembler::icy(Register r1, const MemOperand& opnd) { | 2551 void Assembler::icy(Register r1, const MemOperand& opnd) { |
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2728 Register::from_code(r2.code())); | 2729 Register::from_code(r2.code())); |
2729 } | 2730 } |
2730 | 2731 |
2731 // Store Double (64) | 2732 // Store Double (64) |
2732 void Assembler::std(DoubleRegister r1, const MemOperand& opnd) { | 2733 void Assembler::std(DoubleRegister r1, const MemOperand& opnd) { |
2733 rx_form(STD, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2734 rx_form(STD, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2734 } | 2735 } |
2735 | 2736 |
2736 // Store Double (64) | 2737 // Store Double (64) |
2737 void Assembler::stdy(DoubleRegister r1, const MemOperand& opnd) { | 2738 void Assembler::stdy(DoubleRegister r1, const MemOperand& opnd) { |
| 2739 DCHECK(!(opnd.rb().code() == 15 && opnd.offset() < 0)); |
2738 rxy_form(STDY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2740 rxy_form(STDY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2739 } | 2741 } |
2740 | 2742 |
2741 // Store Float (32) | 2743 // Store Float (32) |
2742 void Assembler::ste(DoubleRegister r1, const MemOperand& opnd) { | 2744 void Assembler::ste(DoubleRegister r1, const MemOperand& opnd) { |
2743 rx_form(STE, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2745 rx_form(STE, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2744 } | 2746 } |
2745 | 2747 |
2746 // Store Float (32) | 2748 // Store Float (32) |
2747 void Assembler::stey(DoubleRegister r1, const MemOperand& opnd) { | 2749 void Assembler::stey(DoubleRegister r1, const MemOperand& opnd) { |
| 2750 DCHECK(!(opnd.rb().code() == 15 && opnd.offset() < 0)); |
2748 rxy_form(STEY, r1, opnd.rx(), opnd.rb(), opnd.offset()); | 2751 rxy_form(STEY, r1, opnd.rx(), opnd.rb(), opnd.offset()); |
2749 } | 2752 } |
2750 | 2753 |
2751 // Load Double (64) | 2754 // Load Double (64) |
2752 void Assembler::ld(DoubleRegister r1, const MemOperand& opnd) { | 2755 void Assembler::ld(DoubleRegister r1, const MemOperand& opnd) { |
2753 DCHECK(is_uint12(opnd.offset())); | 2756 DCHECK(is_uint12(opnd.offset())); |
2754 rx_form(LD, r1, opnd.rx(), opnd.rb(), opnd.offset() & 0xfff); | 2757 rx_form(LD, r1, opnd.rx(), opnd.rb(), opnd.offset() & 0xfff); |
2755 } | 2758 } |
2756 | 2759 |
2757 // Load Double (64) | 2760 // Load Double (64) |
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3049 | 3052 |
3050 reloc_info_writer.Write(&rinfo); | 3053 reloc_info_writer.Write(&rinfo); |
3051 } | 3054 } |
3052 | 3055 |
3053 reloc_info_writer.Finish(); | 3056 reloc_info_writer.Finish(); |
3054 } | 3057 } |
3055 | 3058 |
3056 } // namespace internal | 3059 } // namespace internal |
3057 } // namespace v8 | 3060 } // namespace v8 |
3058 #endif // V8_TARGET_ARCH_S390 | 3061 #endif // V8_TARGET_ARCH_S390 |
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