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Unified Diff: runtime/vm/assembler_arm_test.cc

Issue 19290006: Implements ARM SIMD multiplication and subtraction instructions. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 5 months ago
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Index: runtime/vm/assembler_arm_test.cc
===================================================================
--- runtime/vm/assembler_arm_test.cc (revision 25008)
+++ runtime/vm/assembler_arm_test.cc (working copy)
@@ -1736,6 +1736,264 @@
}
+ASSEMBLER_TEST_GENERATE(Vsubqi8, assembler) {
+ if (CPUFeatures::neon_supported()) {
+ __ mov(R0, ShifterOperand(1));
+ __ vmovsr(S0, R0);
+ __ vmovsr(S1, R0);
+ __ vmovsr(S2, R0);
+ __ vmovsr(S3, R0);
regis 2013/07/16 00:23:30 Being picky, but a test using a different value in
zra 2013/07/16 16:11:01 Done.
+ __ mov(R0, ShifterOperand(3));
+ __ vmovsr(S4, R0);
+ __ vmovsr(S5, R0);
+ __ vmovsr(S6, R0);
+ __ vmovsr(S7, R0);
+
+ __ vsubqi(0, Q2, Q1, Q0);
regis 2013/07/16 00:23:30 Comment about the meaning of 0 until you introduce
zra 2013/07/16 16:11:01 Done.
+
+ __ vmovrs(R0, S8);
+ __ vmovrs(R1, S9);
+ __ vmovrs(R2, S10);
+ __ vmovrs(R3, S11);
+
+ __ add(R0, R0, ShifterOperand(R1));
+ __ add(R0, R0, ShifterOperand(R2));
+ __ add(R0, R0, ShifterOperand(R3));
+ __ bx(LR);
+ } else {
+ __ LoadImmediate(R0, 8);
+ __ bx(LR);
+ }
+}
+
+
+ASSEMBLER_TEST_RUN(Vsubqi8, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ EXPECT_EQ(8, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vsubqi16, assembler) {
+ if (CPUFeatures::neon_supported()) {
+ __ mov(R0, ShifterOperand(1));
+ __ vmovsr(S0, R0);
+ __ vmovsr(S1, R0);
+ __ vmovsr(S2, R0);
+ __ vmovsr(S3, R0);
+ __ mov(R0, ShifterOperand(3));
+ __ vmovsr(S4, R0);
+ __ vmovsr(S5, R0);
+ __ vmovsr(S6, R0);
+ __ vmovsr(S7, R0);
+
+ __ vsubqi(1, Q2, Q1, Q0);
regis 2013/07/16 00:23:30 ditto for 1?
zra 2013/07/16 16:11:01 Done.
+
+ __ vmovrs(R0, S8);
+ __ vmovrs(R1, S9);
+ __ vmovrs(R2, S10);
+ __ vmovrs(R3, S11);
+
+ __ add(R0, R0, ShifterOperand(R1));
+ __ add(R0, R0, ShifterOperand(R2));
+ __ add(R0, R0, ShifterOperand(R3));
+ __ bx(LR);
+ } else {
+ __ LoadImmediate(R0, 8);
+ __ bx(LR);
+ }
+}
+
+
+ASSEMBLER_TEST_RUN(Vsubqi16, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ EXPECT_EQ(8, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vsubqi32, assembler) {
+ if (CPUFeatures::neon_supported()) {
+ __ mov(R0, ShifterOperand(1));
+ __ vmovsr(S0, R0);
+ __ vmovsr(S1, R0);
+ __ vmovsr(S2, R0);
+ __ vmovsr(S3, R0);
+ __ mov(R0, ShifterOperand(3));
+ __ vmovsr(S4, R0);
+ __ vmovsr(S5, R0);
+ __ vmovsr(S6, R0);
+ __ vmovsr(S7, R0);
+
+ __ vsubqi(2, Q2, Q1, Q0);
+
+ __ vmovrs(R0, S8);
+ __ vmovrs(R1, S9);
+ __ vmovrs(R2, S10);
+ __ vmovrs(R3, S11);
+
+ __ add(R0, R0, ShifterOperand(R1));
+ __ add(R0, R0, ShifterOperand(R2));
+ __ add(R0, R0, ShifterOperand(R3));
+ __ bx(LR);
+ } else {
+ __ LoadImmediate(R0, 8);
+ __ bx(LR);
+ }
+}
+
+
+ASSEMBLER_TEST_RUN(Vsubqi32, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ EXPECT_EQ(8, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vsubqi64, assembler) {
+ if (CPUFeatures::neon_supported()) {
+ __ mov(R0, ShifterOperand(1));
+ __ vmovsr(S0, R0);
+ __ vmovsr(S2, R0);
+ __ mov(R0, ShifterOperand(3));
+ __ vmovsr(S4, R0);
+ __ vmovsr(S6, R0);
+
+ __ vsubqi(3, Q2, Q1, Q0);
+
+ __ vmovrs(R0, S8);
+ __ vmovrs(R2, S10);
+
+ __ add(R0, R0, ShifterOperand(R2));
+ __ bx(LR);
+ } else {
+ __ LoadImmediate(R0, 4);
+ __ bx(LR);
+ }
+}
+
+
+ASSEMBLER_TEST_RUN(Vsubqi64, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ EXPECT_EQ(4, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vmulqi8, assembler) {
+ if (CPUFeatures::neon_supported()) {
+ __ mov(R0, ShifterOperand(1));
+ __ vmovsr(S0, R0);
+ __ vmovsr(S1, R0);
+ __ vmovsr(S2, R0);
+ __ vmovsr(S3, R0);
+ __ mov(R0, ShifterOperand(2));
+ __ vmovsr(S4, R0);
+ __ vmovsr(S5, R0);
+ __ vmovsr(S6, R0);
+ __ vmovsr(S7, R0);
+
+ __ vmulqi(0, Q2, Q1, Q0);
+
+ __ vmovrs(R0, S8);
+ __ vmovrs(R1, S9);
+ __ vmovrs(R2, S10);
+ __ vmovrs(R3, S11);
+
+ __ add(R0, R0, ShifterOperand(R1));
+ __ add(R0, R0, ShifterOperand(R2));
+ __ add(R0, R0, ShifterOperand(R3));
+ __ bx(LR);
+ } else {
+ __ LoadImmediate(R0, 8);
+ __ bx(LR);
+ }
+}
+
+
+ASSEMBLER_TEST_RUN(Vmulqi8, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ EXPECT_EQ(8, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vmulqi16, assembler) {
+ if (CPUFeatures::neon_supported()) {
+ __ mov(R0, ShifterOperand(1));
+ __ vmovsr(S0, R0);
+ __ vmovsr(S1, R0);
+ __ vmovsr(S2, R0);
+ __ vmovsr(S3, R0);
+ __ mov(R0, ShifterOperand(2));
+ __ vmovsr(S4, R0);
+ __ vmovsr(S5, R0);
+ __ vmovsr(S6, R0);
+ __ vmovsr(S7, R0);
+
+ __ vmulqi(1, Q2, Q1, Q0);
+
+ __ vmovrs(R0, S8);
+ __ vmovrs(R1, S9);
+ __ vmovrs(R2, S10);
+ __ vmovrs(R3, S11);
+
+ __ add(R0, R0, ShifterOperand(R1));
+ __ add(R0, R0, ShifterOperand(R2));
+ __ add(R0, R0, ShifterOperand(R3));
+ __ bx(LR);
+ } else {
+ __ LoadImmediate(R0, 8);
+ __ bx(LR);
+ }
+}
+
+
+ASSEMBLER_TEST_RUN(Vmulqi16, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ EXPECT_EQ(8, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vmulqi32, assembler) {
+ if (CPUFeatures::neon_supported()) {
+ __ mov(R0, ShifterOperand(1));
+ __ vmovsr(S0, R0);
+ __ vmovsr(S1, R0);
+ __ vmovsr(S2, R0);
+ __ vmovsr(S3, R0);
+ __ mov(R0, ShifterOperand(2));
+ __ vmovsr(S4, R0);
+ __ vmovsr(S5, R0);
+ __ vmovsr(S6, R0);
+ __ vmovsr(S7, R0);
+
+ __ vmulqi(2, Q2, Q1, Q0);
+
+ __ vmovrs(R0, S8);
+ __ vmovrs(R1, S9);
+ __ vmovrs(R2, S10);
+ __ vmovrs(R3, S11);
+
+ __ add(R0, R0, ShifterOperand(R1));
+ __ add(R0, R0, ShifterOperand(R2));
+ __ add(R0, R0, ShifterOperand(R3));
+ __ bx(LR);
+ } else {
+ __ LoadImmediate(R0, 8);
+ __ bx(LR);
+ }
+}
+
+
+ASSEMBLER_TEST_RUN(Vmulqi32, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ EXPECT_EQ(8, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
ASSEMBLER_TEST_GENERATE(Vaddqs, assembler) {
if (CPUFeatures::neon_supported()) {
__ LoadSImmediate(S0, 1.0);
@@ -1771,6 +2029,76 @@
}
+ASSEMBLER_TEST_GENERATE(Vsubqs, assembler) {
+ if (CPUFeatures::neon_supported()) {
+ __ LoadSImmediate(S0, 1.0);
+ __ vmovs(S1, S0);
+ __ vmovs(S2, S0);
+ __ vmovs(S3, S0);
+ __ LoadSImmediate(S4, 4.0);
+ __ vmovs(S5, S4);
+ __ vmovs(S6, S4);
+ __ vmovs(S7, S4);
+
+ __ vsubqs(Q2, Q1, Q0);
+
+ __ vadds(S8, S8, S9);
+ __ vadds(S8, S8, S10);
+ __ vadds(S8, S8, S11);
+
+ __ vcvtis(S0, S8);
+ __ vmovrs(R0, S0);
+
+ __ bx(LR);
+ } else {
+ __ LoadImmediate(R0, 12);
+ __ bx(LR);
+ }
+}
+
+
+ASSEMBLER_TEST_RUN(Vsubqs, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ EXPECT_EQ(12, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vmulqs, assembler) {
+ if (CPUFeatures::neon_supported()) {
+ __ LoadSImmediate(S0, 2.0);
+ __ vmovs(S1, S0);
+ __ vmovs(S2, S0);
+ __ vmovs(S3, S0);
+ __ LoadSImmediate(S4, 3.0);
+ __ vmovs(S5, S4);
+ __ vmovs(S6, S4);
+ __ vmovs(S7, S4);
+
+ __ vmulqs(Q2, Q1, Q0);
+
+ __ vadds(S8, S8, S9);
+ __ vadds(S8, S8, S10);
+ __ vadds(S8, S8, S11);
+
+ __ vcvtis(S0, S8);
+ __ vmovrs(R0, S0);
+
+ __ bx(LR);
+ } else {
+ __ LoadImmediate(R0, 42);
regis 2013/07/16 00:23:30 24?
zra 2013/07/16 16:11:01 Done.
+ __ bx(LR);
+ }
+}
+
+
+ASSEMBLER_TEST_RUN(Vmulqs, test) {
+ EXPECT(test != NULL);
+ typedef int (*Tst)();
+ EXPECT_EQ(24, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
// Called from assembler_test.cc.
// LR: return address.
// R0: context.
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