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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/disassembler.h" | 5 #include "vm/disassembler.h" |
| 6 | 6 |
| 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. | 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. |
| 8 #if defined(TARGET_ARCH_ARM) | 8 #if defined(TARGET_ARCH_ARM) |
| 9 #include "platform/assert.h" | 9 #include "platform/assert.h" |
| 10 | 10 |
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| 524 return 8; | 524 return 8; |
| 525 } | 525 } |
| 526 } else if (format[1] == 'v') { // 'svc | 526 } else if (format[1] == 'v') { // 'svc |
| 527 ASSERT(STRING_STARTS_WITH(format, "svc")); | 527 ASSERT(STRING_STARTS_WITH(format, "svc")); |
| 528 buffer_pos_ += OS::SNPrint(current_position_in_buffer(), | 528 buffer_pos_ += OS::SNPrint(current_position_in_buffer(), |
| 529 remaining_size_in_buffer(), | 529 remaining_size_in_buffer(), |
| 530 "0x%x", | 530 "0x%x", |
| 531 instr->SvcField()); | 531 instr->SvcField()); |
| 532 return 3; | 532 return 3; |
| 533 } else if (format[1] == 'z') { | 533 } else if (format[1] == 'z') { |
| 534 // 'sz: Size field of SIMD instruction. | 534 // 'sz: Size field of SIMD instructions. |
| 535 int sz = 8 << (instr->Bits(20, 2)); | 535 int sz = instr->Bits(20, 2); |
| 536 char const* sz_str; | |
| 537 switch (sz) { | |
| 538 case 0: sz_str = "b"; break; | |
| 539 case 1: sz_str = "h"; break; | |
| 540 case 2: sz_str = "w"; break; | |
| 541 case 3: sz_str = "l"; break; | |
| 542 default: sz_str = "?"; break; | |
| 543 } | |
| 536 buffer_pos_ += OS::SNPrint(current_position_in_buffer(), | 544 buffer_pos_ += OS::SNPrint(current_position_in_buffer(), |
| 537 remaining_size_in_buffer(), | 545 remaining_size_in_buffer(), |
| 538 "I%d", | 546 "%s", |
| 539 sz); | 547 sz_str); |
| 540 return 2; | 548 return 2; |
| 541 } else if (format[1] == ' ') { | 549 } else if (format[1] == ' ') { |
| 542 // 's: S field of data processing instructions. | 550 // 's: S field of data processing instructions. |
| 543 if (instr->HasS()) { | 551 if (instr->HasS()) { |
| 544 Print("s"); | 552 Print("s"); |
| 545 } | 553 } |
| 546 return 1; | 554 return 1; |
| 547 } else { | 555 } else { |
| 548 return FormatSRegister(instr, format); | 556 return FormatSRegister(instr, format); |
| 549 } | 557 } |
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| 1263 } else { | 1271 } else { |
| 1264 Unknown(instr); | 1272 Unknown(instr); |
| 1265 } | 1273 } |
| 1266 } | 1274 } |
| 1267 | 1275 |
| 1268 | 1276 |
| 1269 void ARMDecoder::DecodeSIMDDataProcessing(Instr* instr) { | 1277 void ARMDecoder::DecodeSIMDDataProcessing(Instr* instr) { |
| 1270 ASSERT(instr->ConditionField() == kSpecialCondition); | 1278 ASSERT(instr->ConditionField() == kSpecialCondition); |
| 1271 if (instr->Bit(6) == 1) { | 1279 if (instr->Bit(6) == 1) { |
| 1272 if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 0) && | 1280 if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 0) && |
| 1273 (instr->Bit(24) == 0)) { | 1281 (instr->Bits(23, 2) == 0)) { |
| 1274 Format(instr, "vadd.'sz 'qd, 'qn, 'qm"); | 1282 Format(instr, "vaddqi'sz 'qd, 'qn, 'qm"); |
|
regis
2013/07/16 16:57:38
Isn't the 'i' redundant, since it is replaced by b
| |
| 1275 } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 0) && | 1283 } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 0) && |
| 1276 (instr->Bit(24) == 0)) { | 1284 (instr->Bits(23, 2) == 0) && (instr->Bit(21) == 0)) { |
| 1277 Format(instr, "vadd.F32 'qd, 'qn, 'qm"); | 1285 Format(instr, "vaddqs 'qd, 'qn, 'qm"); |
| 1286 } else if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 0) && | |
| 1287 (instr->Bits(23, 2) == 2)) { | |
| 1288 Format(instr, "vsubqi'sz 'qd, 'qn, 'qm"); | |
| 1289 } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 0) && | |
| 1290 (instr->Bits(23, 2) == 0) && (instr->Bit(21) == 1)) { | |
| 1291 Format(instr, "vsubqs 'qd, 'qn, 'qm"); | |
| 1292 } else if ((instr->Bits(8, 4) == 9) && (instr->Bit(4) == 1) && | |
| 1293 (instr->Bits(23, 2) == 0)) { | |
| 1294 Format(instr, "vmulqi'sz 'qd, 'qn, 'qm"); | |
| 1295 } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 1) && | |
| 1296 (instr->Bits(23, 2) == 2) && (instr->Bit(21) == 0)) { | |
| 1297 Format(instr, "vmulqs 'qd, 'qn, 'qm"); | |
| 1278 } else { | 1298 } else { |
| 1279 Unknown(instr); | 1299 Unknown(instr); |
| 1280 } | 1300 } |
| 1281 } else { | 1301 } else { |
| 1282 Unknown(instr); | 1302 Unknown(instr); |
| 1283 } | 1303 } |
| 1284 } | 1304 } |
| 1285 | 1305 |
| 1286 | 1306 |
| 1287 void ARMDecoder::InstructionDecode(uword pc) { | 1307 void ARMDecoder::InstructionDecode(uword pc) { |
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| 1379 human_buffer, | 1399 human_buffer, |
| 1380 sizeof(human_buffer), | 1400 sizeof(human_buffer), |
| 1381 pc); | 1401 pc); |
| 1382 pc += instruction_length; | 1402 pc += instruction_length; |
| 1383 } | 1403 } |
| 1384 } | 1404 } |
| 1385 | 1405 |
| 1386 } // namespace dart | 1406 } // namespace dart |
| 1387 | 1407 |
| 1388 #endif // defined TARGET_ARCH_ARM | 1408 #endif // defined TARGET_ARCH_ARM |
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