Implements ARM SIMD multiplication and subtraction instructions.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
@@ skipping 1228 matching lines @@
   ASSERT((sz >= 0) && (sz <= 3));
   EmitSIMDqqq(B11, sz, qd, qn, qm);
 }
 
 
 void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B8, 0, qd, qn, qm);
 }
 
 
+void Assembler::vsubqi(int sz, QRegister qd, QRegister qn, QRegister qm) {
+  ASSERT((sz >= 0) && (sz <= 3));
+  EmitSIMDqqq(B24 | B11, sz, qd, qn, qm);
+}
+
+
+void Assembler::vsubqs(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B21 | B11 | B10 | B8, 0, qd, qn, qm);
+}
+
+
+void Assembler::vmulqi(int sz, QRegister qd, QRegister qn, QRegister qm) {
+  ASSERT((sz >= 0) && (sz <= 2));
+  EmitSIMDqqq(B11 | B8 | B4, sz, qd, qn, qm);
+}
+
+
+void Assembler::vmulqs(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, 0, qd, qn, qm);
+}
+
+
 void Assembler::svc(uint32_t imm24, Condition cond) {
   ASSERT(cond != kNoCondition);
   ASSERT(imm24 < (1 << 24));
   int32_t encoding = (cond << kConditionShift) | B27 | B26 | B25 | B24 | imm24;
   Emit(encoding);
 }
 
 
 void Assembler::bkpt(uint16_t imm16) {
   // bkpt requires that the cond field is AL.
@@ skipping 1042 matching lines @@
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM