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Issue 192743006: MIPS: Reland "Handle non-power-of-2 divisors in division-like operations". (Closed) Base URL: https://github.com/v8/v8.git@gbl
Patch Set: Created 6 years, 9 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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5699 opcode == BEQL || 5699 opcode == BEQL ||
5700 opcode == BNEL || 5700 opcode == BNEL ||
5701 opcode == BLEZL || 5701 opcode == BLEZL ||
5702 opcode == BGTZL); 5702 opcode == BGTZL);
5703 opcode = (cond == eq) ? BEQ : BNE; 5703 opcode = (cond == eq) ? BEQ : BNE;
5704 instr = (instr & ~kOpcodeMask) | opcode; 5704 instr = (instr & ~kOpcodeMask) | opcode;
5705 masm_.emit(instr); 5705 masm_.emit(instr);
5706 } 5706 }
5707 5707
5708 5708
5709 void MacroAssembler::FlooringDiv(Register result,
5710 Register dividend,
5711 int32_t divisor) {
5712 ASSERT(!dividend.is(result));
5713 ASSERT(!dividend.is(at));
5714 ASSERT(!result.is(at));
5715 MultiplierAndShift ms(divisor);
5716 li(at, Operand(ms.multiplier()));
5717 Mult(dividend, Operand(at));
5718 mfhi(result);
5719 if (divisor > 0 && ms.multiplier() < 0) {
5720 Addu(result, result, Operand(dividend));
5721 }
5722 if (divisor < 0 && ms.multiplier() > 0) {
5723 Subu(result, result, Operand(dividend));
5724 }
5725 if (ms.shift() > 0) {
5726 sra(result, result, ms.shift());
5727 }
5728 }
5729
5730
5709 } } // namespace v8::internal 5731 } } // namespace v8::internal
5710 5732
5711 #endif // V8_TARGET_ARCH_MIPS 5733 #endif // V8_TARGET_ARCH_MIPS
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