Inline Float64x2 methods with zero arguments

runtime/vm/intermediate_language_arm.cc

Index: runtime/vm/intermediate_language_arm.cc
diff --git a/runtime/vm/intermediate_language_arm.cc b/runtime/vm/intermediate_language_arm.cc
index 499244f5543875935b8a9a1778f420b7c89ac6a1..dc33f6eec9f81afe52b9decb0bf0a0763fb8a4c0 100644
--- a/runtime/vm/intermediate_language_arm.cc
+++ b/runtime/vm/intermediate_language_arm.cc
@@ -4026,6 +4026,70 @@ void Float32x4ToFloat64x2Instr::EmitNativeCode(FlowGraphCompiler* compiler) {
 }
 
 
+LocationSummary* Float64x2ZeroArgInstr::MakeLocationSummary(bool opt) const {
+  const intptr_t kNumInputs = 1;
+  const intptr_t kNumTemps = 0;
+  LocationSummary* summary =
+      new LocationSummary(kNumInputs, kNumTemps, LocationSummary::kNoCall);
+  summary->set_in(0, Location::RequiresFpuRegister());

[zra, 2014/03/10 20:43:38]

Location::RequiresFpuRegister(Q6) if op_kind() == GetSignMask

[Cutch, 2014/03/10 20:52:47]

Done.

+  if (representation() == kTagged) {
+    ASSERT(op_kind() == MethodRecognizer::kFloat64x2GetSignMask);
+    summary->set_out(Location::RequiresRegister());
+    summary->AddTemp(Location::RequiresRegister());
+  } else {
+    summary->set_out(Location::RequiresFpuRegister());
+  }
+  return summary;
+}
+
+
+void Float64x2ZeroArgInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
+  QRegister q = locs()->in(0).fpu_reg();
+
+  if ((op_kind() == MethodRecognizer::kFloat64x2GetSignMask)) {
+    DRegister dvalue0 = EvenDRegisterOf(q);
+    DRegister dvalue1 = OddDRegisterOf(q);
+
+    Register out = locs()->out().reg();
+    Register temp = locs()->temp(0).reg();
+
+    // Upper 32-bits of X lane.
+    __ vmovrs(out, OddSRegisterOf(dvalue0));

[zra, 2014/03/10 20:43:38]

Grabbing the S components means we need a low-numbered Q register, e.g. Q6.

[Cutch, 2014/03/10 20:52:47]

Done.

+    __ Lsr(out, out, 31);
+    // Upper 32-bits of Y lane.
+    __ vmovrs(temp, OddSRegisterOf(dvalue1));
+    __ Lsr(temp, temp, 31);
+    __ orr(out, out, ShifterOperand(temp, LSL, 1));
+    // Tag.
+    __ SmiTag(out);
+    return;
+  }
+  ASSERT(representation() == kUnboxedFloat64x2);
+  QRegister r = locs()->out().fpu_reg();
+
+  DRegister dvalue0 = EvenDRegisterOf(q);
+  DRegister dvalue1 = OddDRegisterOf(q);
+  DRegister dresult0 = EvenDRegisterOf(r);
+  DRegister dresult1 = OddDRegisterOf(r);
+
+  switch (op_kind()) {
+    case MethodRecognizer::kFloat64x2Negate:
+      __ vnegd(dresult0, dvalue0);
+      __ vnegd(dresult1, dvalue1);
+      break;
+    case MethodRecognizer::kFloat64x2Abs:
+      __ vabsd(dresult0, dvalue0);
+      __ vabsd(dresult1, dvalue1);
+      break;
+    case MethodRecognizer::kFloat64x2Sqrt:
+      __ vsqrtd(dresult0, dvalue0);
+      __ vsqrtd(dresult1, dvalue1);
+      break;
+    default: UNREACHABLE();
+  }
+}
+
+
 LocationSummary* Int32x4BoolConstructorInstr::MakeLocationSummary(
     bool opt) const {
   const intptr_t kNumInputs = 4;