Merges ARM load/store type enums into one enum.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
@@ skipping 1201 matching lines @@
 void Assembler::vmstat(Condition cond) {  // VMRS APSR_nzcv, FPSCR
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
                      (static_cast<int32_t>(PC)*B12) |
                      B11 | B9 | B4;
   Emit(encoding);
 }
 
 
-void Assembler::EmitSIMDqqq(int32_t opcode, int sz,
+void Assembler::EmitSIMDqqq(int32_t opcode, OperandSize size,
                             QRegister qd, QRegister qn, QRegister qm) {
+  int sz = 0;
+  switch (size) {
+    case kByte:
+    case kUnsignedByte:
+      sz = 0;
+      break;
+    case kHalfword:
+    case kUnsignedHalfword:
+      sz = 1;
+      break;
+    case kWord:
+    case kUnsignedWord:
+      sz = 2;
+      break;
+    case kWordPair:
+      sz = 3;
+      break;
+    case kSWord:
+    case kDWord:
+      sz = 0;
+      break;
+    default:
+      UNREACHABLE();
+      break;
+  }
   int32_t encoding =
       (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
       B25 | B6 |
       opcode | ((sz & 0x3) * B20) |
       ((static_cast<int32_t>(qd * 2) >> 4)*B22) |
       ((static_cast<int32_t>(qn * 2) & 0xf)*B16) |
       ((static_cast<int32_t>(qd * 2) & 0xf)*B12) |
       ((static_cast<int32_t>(qn * 2) >> 4)*B7) |
       ((static_cast<int32_t>(qm * 2) >> 4)*B5) |
       (static_cast<int32_t>(qm * 2) & 0xf);
   Emit(encoding);
 }
 
 
-void Assembler::vaddqi(int sz, QRegister qd, QRegister qn, QRegister qm) {
-  ASSERT((sz >= 0) && (sz <= 3));
+void Assembler::vaddqi(OperandSize sz,
+                       QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11, sz, qd, qn, qm);
 }
 
 
 void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
-  EmitSIMDqqq(B11 | B10 | B8, 0, qd, qn, qm);
+  EmitSIMDqqq(B11 | B10 | B8, kSWord, qd, qn, qm);
 }
 
 
-void Assembler::vsubqi(int sz, QRegister qd, QRegister qn, QRegister qm) {
-  ASSERT((sz >= 0) && (sz <= 3));
+void Assembler::vsubqi(OperandSize sz,
+                       QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11, sz, qd, qn, qm);
 }
 
 
 void Assembler::vsubqs(QRegister qd, QRegister qn, QRegister qm) {
-  EmitSIMDqqq(B21 | B11 | B10 | B8, 0, qd, qn, qm);
+  EmitSIMDqqq(B21 | B11 | B10 | B8, kSWord, qd, qn, qm);
 }
 
 
-void Assembler::vmulqi(int sz, QRegister qd, QRegister qn, QRegister qm) {
-  ASSERT((sz >= 0) && (sz <= 2));
+void Assembler::vmulqi(OperandSize sz,
+                       QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B8 | B4, sz, qd, qn, qm);
 }
 
 
 void Assembler::vmulqs(QRegister qd, QRegister qn, QRegister qm) {
-  EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, 0, qd, qn, qm);
+  EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::svc(uint32_t imm24, Condition cond) {
   ASSERT(cond != kNoCondition);
   ASSERT(imm24 < (1 << 24));
   int32_t encoding = (cond << kConditionShift) | B27 | B26 | B25 | B24 | imm24;
   Emit(encoding);
 }
 
@@ skipping 52 matching lines @@
   }
 }
 
 
 // Uses a code sequence that can easily be decoded.
 void Assembler::LoadWordFromPoolOffset(Register rd,
                                        int32_t offset,
                                        Condition cond) {
   ASSERT(rd != PP);
   int32_t offset_mask = 0;
-  if (Address::CanHoldLoadOffset(kLoadWord, offset, &offset_mask)) {
+  if (Address::CanHoldLoadOffset(kWord, offset, &offset_mask)) {
     ldr(rd, Address(PP, offset), cond);
   } else {
     int32_t offset_hi = offset & ~offset_mask;  // signed
     uint32_t offset_lo = offset & offset_mask;  // unsigned
     // Inline a simplified version of AddImmediate(rd, PP, offset_hi).
     ShifterOperand shifter_op;
     if (ShifterOperand::CanHold(offset_hi, &shifter_op)) {
       add(rd, PP, shifter_op, cond);
     } else {
       movw(rd, Utils::Low16Bits(offset_hi));
       const uint16_t value_high = Utils::High16Bits(offset_hi);
       if (value_high != 0) {
         movt(rd, value_high, cond);
       }
       add(rd, PP, ShifterOperand(LR), cond);
     }
     ldr(rd, Address(rd, offset_lo), cond);
   }
 }
 
 
 void Assembler::LoadPoolPointer() {
   const intptr_t object_pool_pc_dist =
      Instructions::HeaderSize() - Instructions::object_pool_offset() +
      CodeSize() + Instr::kPCReadOffset;
-  LoadFromOffset(kLoadWord, PP, PC, -object_pool_pc_dist);
+  LoadFromOffset(kWord, PP, PC, -object_pool_pc_dist);
 }
 
 
 void Assembler::LoadObject(Register rd, const Object& object, Condition cond) {
   // Smis and VM heap objects are never relocated; do not use object pool.
   if (object.IsSmi()) {
     LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()), cond);
   } else if (object.InVMHeap()) {
     // Make sure that class CallPattern is able to decode this load immediate.
     const int32_t object_raw = reinterpret_cast<int32_t>(object.raw());
@@ skipping 115 matching lines @@
       RawObject::kClassIdTagBit / kBitsPerByte;
   ldrh(result, FieldAddress(object, class_id_offset));
 }
 
 
 void Assembler::LoadClassById(Register result, Register class_id) {
   ASSERT(result != class_id);
   ldr(result, FieldAddress(CTX, Context::isolate_offset()));
   const intptr_t table_offset_in_isolate =
       Isolate::class_table_offset() + ClassTable::table_offset();
-  LoadFromOffset(kLoadWord, result, result, table_offset_in_isolate);
+  LoadFromOffset(kWord, result, result, table_offset_in_isolate);
   ldr(result, Address(result, class_id, LSL, 2));
 }
 
 
 void Assembler::LoadClass(Register result, Register object, Register scratch) {
   ASSERT(scratch != result);
   LoadClassId(scratch, object);
 
   ldr(result, FieldAddress(CTX, Context::isolate_offset()));
   const intptr_t table_offset_in_isolate =
       Isolate::class_table_offset() + ClassTable::table_offset();
-  LoadFromOffset(kLoadWord, result, result, table_offset_in_isolate);
+  LoadFromOffset(kWord, result, result, table_offset_in_isolate);
   ldr(result, Address(result, scratch, LSL, 2));
 }
 
 
 void Assembler::CompareClassId(Register object,
                                intptr_t class_id,
                                Register scratch) {
   LoadClassId(scratch, object);
   CompareImmediate(scratch, class_id);
 }
 
 
 void Assembler::Bind(Label* label) {
   ASSERT(!label->IsBound());
   int bound_pc = buffer_.Size();
   while (label->IsLinked()) {
     int32_t position = label->Position();
     int32_t next = buffer_.Load<int32_t>(position);
     int32_t encoded = Assembler::EncodeBranchOffset(bound_pc - position, next);
     buffer_.Store<int32_t>(position, encoded);
     label->position_ = Assembler::DecodeBranchOffset(next);
   }
   label->BindTo(bound_pc);
 }
 
 
-bool Address::CanHoldLoadOffset(LoadOperandType type,
+bool Address::CanHoldLoadOffset(OperandSize type,
                                 int32_t offset,
                                 int32_t* offset_mask) {
   switch (type) {
-    case kLoadSignedByte:
-    case kLoadSignedHalfword:
-    case kLoadUnsignedHalfword:
-    case kLoadWordPair: {
+    case kByte:
+    case kHalfword:
+    case kUnsignedHalfword:
+    case kWordPair: {
       *offset_mask = 0xff;
       return Utils::IsAbsoluteUint(8, offset);  // Addressing mode 3.
     }
-    case kLoadUnsignedByte:
-    case kLoadWord: {
+    case kUnsignedByte:
+    case kWord: {
       *offset_mask = 0xfff;
       return Utils::IsAbsoluteUint(12, offset);  // Addressing mode 2.
     }
-    case kLoadSWord:
-    case kLoadDWord: {
+    case kSWord:
+    case kDWord: {
       *offset_mask = 0x3fc;  // Multiple of 4.
       // VFP addressing mode.
       return (Utils::IsAbsoluteUint(10, offset) && Utils::IsAligned(offset, 4));
     }
     default: {
       UNREACHABLE();
       return false;
     }
   }
 }
 
 
-bool Address::CanHoldStoreOffset(StoreOperandType type,
+bool Address::CanHoldStoreOffset(OperandSize type,
                                  int32_t offset,
                                  int32_t* offset_mask) {
   switch (type) {
-    case kStoreHalfword:
-    case kStoreWordPair: {
+    case kHalfword:
+    case kWordPair: {
       *offset_mask = 0xff;
       return Utils::IsAbsoluteUint(8, offset);  // Addressing mode 3.
     }
-    case kStoreByte:
-    case kStoreWord: {
+    case kByte:
+    case kWord: {
       *offset_mask = 0xfff;
       return Utils::IsAbsoluteUint(12, offset);  // Addressing mode 2.
     }
-    case kStoreSWord:
-    case kStoreDWord: {
+    case kSWord:
+    case kDWord: {
       *offset_mask = 0x3fc;  // Multiple of 4.
       // VFP addressing mode.
       return (Utils::IsAbsoluteUint(10, offset) && Utils::IsAligned(offset, 4));
     }
     default: {
       UNREACHABLE();
       return false;
     }
   }
 }
@@ skipping 120 matching lines @@
   // TODO(regis): Revisit this code sequence.
   LoadImmediate(IP, label->address());  // Target address is never patched.
   str(PC, ad);
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
 
 
 void Assembler::BranchLinkOffset(Register base, int32_t offset) {
   ASSERT(base != PC);
   ASSERT(base != IP);
-  LoadFromOffset(kLoadWord, IP, base, offset);
+  LoadFromOffset(kWord, IP, base, offset);
   blx(IP);  // Use blx instruction so that the return branch prediction works.
 }
 
 
 void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
   ShifterOperand shifter_op;
   if (ShifterOperand::CanHold(value, &shifter_op)) {
     mov(rd, shifter_op, cond);
   } else if (ShifterOperand::CanHold(~value, &shifter_op)) {
     mvn(rd, shifter_op, cond);
@@ skipping 26 matching lines @@
     // A scratch register and IP are needed to load an arbitrary double.
     ASSERT(scratch != kNoRegister);
     int64_t imm64 = bit_cast<int64_t, double>(value);
     LoadImmediate(IP, Utils::Low32Bits(imm64), cond);
     LoadImmediate(scratch, Utils::High32Bits(imm64), cond);
     vmovdrr(dd, IP, scratch, cond);
   }
 }
 
 
-void Assembler::LoadFromOffset(LoadOperandType type,
+void Assembler::LoadFromOffset(OperandSize type,
                                Register reg,
                                Register base,
                                int32_t offset,
                                Condition cond) {
   int32_t offset_mask = 0;
   if (!Address::CanHoldLoadOffset(type, offset, &offset_mask)) {
     ASSERT(base != IP);
     AddImmediate(IP, base, offset & ~offset_mask, cond);
     base = IP;
     offset = offset & offset_mask;
   }
   switch (type) {
-    case kLoadSignedByte:
+    case kByte:
       ldrsb(reg, Address(base, offset), cond);
       break;
-    case kLoadUnsignedByte:
+    case kUnsignedByte:
       ldrb(reg, Address(base, offset), cond);
       break;
-    case kLoadSignedHalfword:
+    case kHalfword:
       ldrsh(reg, Address(base, offset), cond);
       break;
-    case kLoadUnsignedHalfword:
+    case kUnsignedHalfword:
       ldrh(reg, Address(base, offset), cond);
       break;
-    case kLoadWord:
+    case kWord:
       ldr(reg, Address(base, offset), cond);
       break;
-    case kLoadWordPair:
+    case kWordPair:
       ldrd(reg, Address(base, offset), cond);
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
-void Assembler::StoreToOffset(StoreOperandType type,
+void Assembler::StoreToOffset(OperandSize type,
                               Register reg,
                               Register base,
                               int32_t offset,
                               Condition cond) {
   int32_t offset_mask = 0;
   if (!Address::CanHoldStoreOffset(type, offset, &offset_mask)) {
     ASSERT(reg != IP);
     ASSERT(base != IP);
     AddImmediate(IP, base, offset & ~offset_mask, cond);
     base = IP;
     offset = offset & offset_mask;
   }
   switch (type) {
-    case kStoreByte:
+    case kByte:
       strb(reg, Address(base, offset), cond);
       break;
-    case kStoreHalfword:
+    case kHalfword:
       strh(reg, Address(base, offset), cond);
       break;
-    case kStoreWord:
+    case kWord:
       str(reg, Address(base, offset), cond);
       break;
-    case kStoreWordPair:
+    case kWordPair:
       strd(reg, Address(base, offset), cond);
       break;
     default:
       UNREACHABLE();
   }
 }
 
 
 void Assembler::LoadSFromOffset(SRegister reg,
                                 Register base,
                                 int32_t offset,
                                 Condition cond) {
   int32_t offset_mask = 0;
-  if (!Address::CanHoldLoadOffset(kLoadSWord, offset, &offset_mask)) {
+  if (!Address::CanHoldLoadOffset(kSWord, offset, &offset_mask)) {
     ASSERT(base != IP);
     AddImmediate(IP, base, offset & ~offset_mask, cond);
     base = IP;
     offset = offset & offset_mask;
   }
   vldrs(reg, Address(base, offset), cond);
 }
 
 
 void Assembler::StoreSToOffset(SRegister reg,
                                Register base,
                                int32_t offset,
                                Condition cond) {
   int32_t offset_mask = 0;
-  if (!Address::CanHoldStoreOffset(kStoreSWord, offset, &offset_mask)) {
+  if (!Address::CanHoldStoreOffset(kSWord, offset, &offset_mask)) {
     ASSERT(base != IP);
     AddImmediate(IP, base, offset & ~offset_mask, cond);
     base = IP;
     offset = offset & offset_mask;
   }
   vstrs(reg, Address(base, offset), cond);
 }
 
 
 void Assembler::LoadDFromOffset(DRegister reg,
                                 Register base,
                                 int32_t offset,
                                 Condition cond) {
   int32_t offset_mask = 0;
-  if (!Address::CanHoldLoadOffset(kLoadDWord, offset, &offset_mask)) {
+  if (!Address::CanHoldLoadOffset(kDWord, offset, &offset_mask)) {
     ASSERT(base != IP);
     AddImmediate(IP, base, offset & ~offset_mask, cond);
     base = IP;
     offset = offset & offset_mask;
   }
   vldrd(reg, Address(base, offset), cond);
 }
 
 
 void Assembler::StoreDToOffset(DRegister reg,
                                Register base,
                                int32_t offset,
                                Condition cond) {
   int32_t offset_mask = 0;
-  if (!Address::CanHoldStoreOffset(kStoreDWord, offset, &offset_mask)) {
+  if (!Address::CanHoldStoreOffset(kDWord, offset, &offset_mask)) {
     ASSERT(base != IP);
     AddImmediate(IP, base, offset & ~offset_mask, cond);
     base = IP;
     offset = offset & offset_mask;
   }
   vstrd(reg, Address(base, offset), cond);
 }
 
 
 void Assembler::AddImmediate(Register rd, int32_t value, Condition cond) {
@@ skipping 419 matching lines @@
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM