Fix cctest/test-cpu-profiler/FunctionApplySample fakiness on ARM simulator

src/arm/simulator-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1516 matching lines @@
   while (bit_vector != 0) {
     if ((bit_vector & 1) != 0) {
       count++;
     }
     bit_vector >>= 1;
   }
   return count;
 }
 
 
-void Simulator::ProcessPUW(Instruction* instr,
-                           int num_regs,
-                           int reg_size,
-                           intptr_t* start_address,
-                           intptr_t* end_address) {
+int32_t Simulator::ProcessPU(Instruction* instr,
+                             int num_regs,
+                             int reg_size,
+                             intptr_t* start_address,
+                             intptr_t* end_address) {
   int rn = instr->RnValue();
   int32_t rn_val = get_register(rn);
   switch (instr->PUField()) {
     case da_x: {
       UNIMPLEMENTED();
       break;
     }
     case ia_x: {
       *start_address = rn_val;
       *end_address = rn_val + (num_regs * reg_size) - reg_size;
@@ skipping 10 matching lines @@
       *start_address = rn_val + reg_size;
       *end_address = rn_val + (num_regs * reg_size);
       rn_val = *end_address;
       break;
     }
     default: {
       UNREACHABLE();
       break;
     }
   }
-  if (instr->HasW()) {
-    set_register(rn, rn_val);
-  }
+  return rn_val;
 }
 
 
 // Addressing Mode 4 - Load and Store Multiple
 void Simulator::HandleRList(Instruction* instr, bool load) {
   int rlist = instr->RlistValue();
   int num_regs = count_bits(rlist);
 
   intptr_t start_address = 0;
   intptr_t end_address = 0;
-  ProcessPUW(instr, num_regs, kPointerSize, &start_address, &end_address);
+  int32_t rn_val =
+      ProcessPU(instr, num_regs, kPointerSize, &start_address, &end_address);
 
   intptr_t* address = reinterpret_cast<intptr_t*>(start_address);
   // Catch null pointers a little earlier.
   ASSERT(start_address > 8191 || start_address < 0);
   int reg = 0;
   while (rlist != 0) {
     if ((rlist & 1) != 0) {
       if (load) {
         set_register(reg, *address);
       } else {
         *address = get_register(reg);
       }
       address += 1;
     }
     reg++;
     rlist >>= 1;
   }
   ASSERT(end_address == ((intptr_t)address) - 4);
+  if (instr->HasW()) {
+    set_register(instr->RnValue(), rn_val);
+  }
 }
 
 
 // Addressing Mode 6 - Load and Store Multiple Coprocessor registers.
 void Simulator::HandleVList(Instruction* instr) {
   VFPRegPrecision precision =
       (instr->SzValue() == 0) ? kSinglePrecision : kDoublePrecision;
   int operand_size = (precision == kSinglePrecision) ? 4 : 8;
 
   bool load = (instr->VLValue() == 0x1);
 
   int vd;
   int num_regs;
   vd = instr->VFPDRegValue(precision);
   if (precision == kSinglePrecision) {
     num_regs = instr->Immed8Value();
   } else {
     num_regs = instr->Immed8Value() / 2;
   }
 
   intptr_t start_address = 0;
   intptr_t end_address = 0;
-  ProcessPUW(instr, num_regs, operand_size, &start_address, &end_address);
+  int32_t rn_val =
+      ProcessPU(instr, num_regs, operand_size, &start_address, &end_address);
 
   intptr_t* address = reinterpret_cast<intptr_t*>(start_address);
   for (int reg = vd; reg < vd + num_regs; reg++) {
     if (precision == kSinglePrecision) {
       if (load) {
         set_s_register_from_sinteger(
             reg, ReadW(reinterpret_cast<int32_t>(address), instr));
       } else {
         WriteW(reinterpret_cast<int32_t>(address),
                get_sinteger_from_s_register(reg), instr);
@@ skipping 12 matching lines @@
         int32_t data[2];
         double d = get_double_from_d_register(reg);
         OS::MemCopy(data, &d, 8);
         WriteW(reinterpret_cast<int32_t>(address), data[0], instr);
         WriteW(reinterpret_cast<int32_t>(address + 1), data[1], instr);
       }
       address += 2;
     }
   }
   ASSERT(reinterpret_cast<intptr_t>(address) - operand_size == end_address);
+  if (instr->HasW()) {
+    set_register(instr->RnValue(), rn_val);
+  }
 }
 
 
 // Calls into the V8 runtime are based on this very simple interface.
 // Note: To be able to return two values from some calls the code in runtime.cc
 // uses the ObjectPair which is essentially two 32-bit values stuffed into a
 // 64-bit value. With the code below we assume that all runtime calls return
 // 64 bits of result. If they don't, the r1 result register contains a bogus
 // value, which is fine because it is caller-saved.
 typedef int64_t (*SimulatorRuntimeCall)(int32_t arg0,
@@ skipping 2221 matching lines @@
   uintptr_t address = *stack_slot;
   set_register(sp, current_sp + sizeof(uintptr_t));
   return address;
 }
 
 } }  // namespace v8::internal
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_ARM