[arm64] Use 'dc civac' to work around some errata.

src/arm64/cpu-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // CPU specific code for arm independent of OS goes here.
 
 #if V8_TARGET_ARCH_ARM64
 
 #include "src/arm64/utils-arm64.h"
 #include "src/assembler.h"
@@ skipping 40 matching lines @@
   // Cache line sizes are always a power of 2.
   DCHECK(CountSetBits(dsize, 64) == 1);
   DCHECK(CountSetBits(isize, 64) == 1);
   uintptr_t dstart = start & ~(dsize - 1);
   uintptr_t istart = start & ~(isize - 1);
   uintptr_t end = start + length;
 
   __asm__ __volatile__ (  // NOLINT
     // Clean every line of the D cache containing the target data.
     "0:                                \n\t"
-    // dc      : Data Cache maintenance
-    //    c    : Clean
-    //     va  : by (Virtual) Address
-    //       u : to the point of Unification
-    // The point of unification for a processor is the point by which the
-    // instruction and data caches are guaranteed to see the same copy of a
-    // memory location. See ARM DDI 0406B page B2-12 for more information.
-    "dc   cvau, %[dline]                \n\t"
+    // dc       : Data Cache maintenance
+    //    c     : Clean
+    //     i    : Invalidate
+    //      va  : by (Virtual) Address
+    //        c : to the point of Coherency
+    // See ARM DDI 0406B page B2-12 for more information.
+    // We would prefer to use "cvau" (clean to the point of unification) here
+    // but we use "civac" to work around Cortex-A53 errata 819472, 826319,
+    // 827319 and 824069.
+    "dc   civac, %[dline]               \n\t"
     "add  %[dline], %[dline], %[dsize]  \n\t"
     "cmp  %[dline], %[end]              \n\t"
     "b.lt 0b                            \n\t"
     // Barrier to make sure the effect of the code above is visible to the rest
     // of the world.
     // dsb    : Data Synchronisation Barrier
     //    ish : Inner SHareable domain
     // The point of unification for an Inner Shareable shareability domain is
     // the point by which the instruction and data caches of all the processors
     // in that Inner Shareable shareability domain are guaranteed to see the
@@ skipping 26 matching lines @@
     // move this code before the code is generated.
     : "cc", "memory"
   );  // NOLINT
 #endif  // V8_HOST_ARCH_ARM64
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM64