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Side by Side Diff: src/IceAssemblerX86BaseImpl.h

Issue 1917863004: Subzero. X86. Uses pshufb for shufflevector lowering. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Deterministic table name." Created 4 years, 8 months ago
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1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=// 1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=//
2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
3 // for details. All rights reserved. Use of this source code is governed by a 3 // for details. All rights reserved. Use of this source code is governed by a
4 // BSD-style license that can be found in the LICENSE file. 4 // BSD-style license that can be found in the LICENSE file.
5 // 5 //
6 // Modified by the Subzero authors. 6 // Modified by the Subzero authors.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // The Subzero Code Generator 10 // The Subzero Code Generator
(...skipping 1517 matching lines...) Expand 10 before | Expand all | Expand 10 after
1528 const Immediate &imm) { 1528 const Immediate &imm) {
1529 // Load 32-bit immediate value into tmp1. 1529 // Load 32-bit immediate value into tmp1.
1530 mov(IceType_i32, tmp1, imm); 1530 mov(IceType_i32, tmp1, imm);
1531 // Move value from tmp1 into dst. 1531 // Move value from tmp1 into dst.
1532 movd(IceType_i32, dst, tmp1); 1532 movd(IceType_i32, dst, tmp1);
1533 // Broadcast low lane into other three lanes. 1533 // Broadcast low lane into other three lanes.
1534 shufps(RexTypeIrrelevant, dst, dst, Immediate(0x0)); 1534 shufps(RexTypeIrrelevant, dst, dst, Immediate(0x0));
1535 } 1535 }
1536 1536
1537 template <typename TraitsType> 1537 template <typename TraitsType>
1538 void AssemblerX86Base<TraitsType>::pshufb(Type /* Ty */, XmmRegister dst,
1539 XmmRegister src) {
1540 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
1541 emitUint8(0x66);
1542 emitRexRB(RexTypeIrrelevant, dst, src);
1543 emitUint8(0x0F);
1544 emitUint8(0x38);
1545 emitUint8(0x00);
1546 emitXmmRegisterOperand(dst, src);
1547 }
1548
1549 template <typename TraitsType>
1550 void AssemblerX86Base<TraitsType>::pshufb(Type /* Ty */, XmmRegister dst,
1551 const Address &src) {
1552 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
1553 emitUint8(0x66);
1554 emitAddrSizeOverridePrefix();
1555 emitRex(RexTypeIrrelevant, src, dst);
1556 emitUint8(0x0F);
1557 emitUint8(0x38);
1558 emitUint8(0x00);
1559 emitOperand(gprEncoding(dst), src);
1560 }
1561
1562 template <typename TraitsType>
1538 void AssemblerX86Base<TraitsType>::pshufd(Type /* Ty */, XmmRegister dst, 1563 void AssemblerX86Base<TraitsType>::pshufd(Type /* Ty */, XmmRegister dst,
1539 XmmRegister src, 1564 XmmRegister src,
1540 const Immediate &imm) { 1565 const Immediate &imm) {
1541 AssemblerBuffer::EnsureCapacity ensured(&Buffer); 1566 AssemblerBuffer::EnsureCapacity ensured(&Buffer);
1542 emitUint8(0x66); 1567 emitUint8(0x66);
1543 emitRexRB(RexTypeIrrelevant, dst, src); 1568 emitRexRB(RexTypeIrrelevant, dst, src);
1544 emitUint8(0x0F); 1569 emitUint8(0x0F);
1545 emitUint8(0x70); 1570 emitUint8(0x70);
1546 emitXmmRegisterOperand(dst, src); 1571 emitXmmRegisterOperand(dst, src);
1547 assert(imm.is_uint8()); 1572 assert(imm.is_uint8());
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3558 (void)shifter; 3583 (void)shifter;
3559 if (Ty == IceType_i16) 3584 if (Ty == IceType_i16)
3560 emitOperandSizeOverride(); 3585 emitOperandSizeOverride();
3561 emitRexB(Ty, operand.rm()); 3586 emitRexB(Ty, operand.rm());
3562 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3); 3587 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3);
3563 emitOperand(rm, operand); 3588 emitOperand(rm, operand);
3564 } 3589 }
3565 3590
3566 } // end of namespace X86NAMESPACE 3591 } // end of namespace X86NAMESPACE
3567 } // end of namespace Ice 3592 } // end of namespace Ice
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