[turbofan] Single entry into deferred regions

src/compiler/instruction.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/common-operator.h"
 #include "src/compiler/graph.h"
 #include "src/compiler/instruction.h"
 #include "src/compiler/schedule.h"
 #include "src/compiler/state-values-utils.h"
 
@@ skipping 610 matching lines @@
   for (BasicBlockVector::const_iterator it = schedule->rpo_order()->begin();
        it != schedule->rpo_order()->end(); ++it, ++rpo_number) {
     DCHECK(!(*blocks)[rpo_number]);
     DCHECK(GetRpo(*it).ToSize() == rpo_number);
     (*blocks)[rpo_number] = InstructionBlockFor(zone, *it);
   }
   ComputeAssemblyOrder(blocks);
   return blocks;
 }
 
-void InstructionSequence::ValidateEdgeSplitForm() {
+void InstructionSequence::ValidateEdgeSplitForm() const {
   // Validate blocks are in edge-split form: no block with multiple successors
   // has an edge to a block (== a successor) with more than one predecessors.
   for (const InstructionBlock* block : instruction_blocks()) {
     if (block->SuccessorCount() > 1) {
       for (const RpoNumber& successor_id : block->successors()) {
         const InstructionBlock* successor = InstructionBlockAt(successor_id);
         // Expect precisely one predecessor: "block".
         CHECK(successor->PredecessorCount() == 1 &&
               successor->predecessors()[0] == block->rpo_number());
       }
     }
   }
 }
 
-void InstructionSequence::ValidateDeferredBlockExitPaths() {
+void InstructionSequence::ValidateDeferredBlockExitPaths() const {
   // A deferred block with more than one successor must have all its successors
   // deferred.
   for (const InstructionBlock* block : instruction_blocks()) {
     if (!block->IsDeferred() || block->SuccessorCount() <= 1) continue;
     for (RpoNumber successor_id : block->successors()) {
       CHECK(InstructionBlockAt(successor_id)->IsDeferred());
     }
   }
 }
 
-void InstructionSequence::ValidateSSA() {
+void InstructionSequence::ValidateDeferredBlockEntryPaths() const {
+  // If a deferred block has multiple predecessors, they have to
+  // all be deferred. Otherwise, we can run into a situation where a range
+  // that spills only in deferred blocks inserts its spill in the block, but
+  // other ranges need moves inserted by ResolveControlFlow in the predecessors,
+  // which may clobber the register of this range.
+  for (const InstructionBlock* block : instruction_blocks()) {
+    if (!block->IsDeferred() || block->PredecessorCount() <= 1) continue;
+    for (RpoNumber predecessor_id : block->predecessors()) {
+      CHECK(InstructionBlockAt(predecessor_id)->IsDeferred());
+    }
+  }
+}
+
+void InstructionSequence::ValidateSSA() const {
   // TODO(mtrofin): We could use a local zone here instead.
   BitVector definitions(VirtualRegisterCount(), zone());
   for (const Instruction* instruction : *this) {
     for (size_t i = 0; i < instruction->OutputCount(); ++i) {
       const InstructionOperand* output = instruction->OutputAt(i);
       int vreg = (output->IsConstant())
                      ? ConstantOperand::cast(output)->virtual_register()
                      : UnallocatedOperand::cast(output)->virtual_register();
       CHECK(!definitions.Contains(vreg));
       definitions.Add(vreg);
@@ skipping 344 matching lines @@
   }
   for (int i = 0; i < code.InstructionBlockCount(); i++) {
     printable.sequence_->PrintBlock(printable.register_configuration_, i);
   }
   return os;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8