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1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// | 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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2301 break; | 2301 break; |
2302 case IceType_i8: | 2302 case IceType_i8: |
2303 Eax = Traits::RegisterSet::Reg_al; | 2303 Eax = Traits::RegisterSet::Reg_al; |
2304 Edx = Traits::RegisterSet::Reg_ah; | 2304 Edx = Traits::RegisterSet::Reg_ah; |
2305 break; | 2305 break; |
2306 } | 2306 } |
2307 T_edx = makeReg(Ty, Edx); | 2307 T_edx = makeReg(Ty, Edx); |
2308 _mov(T_edx, Ctx->getConstantZero(Ty)); | 2308 _mov(T_edx, Ctx->getConstantZero(Ty)); |
2309 _mov(T, Src0, Eax); | 2309 _mov(T, Src0, Eax); |
2310 _div(T_edx, Src1, T); | 2310 _div(T_edx, Src1, T); |
| 2311 if (Ty == IceType_i8) { |
| 2312 // Register ah must be moved into one of {al,bl,cl,dl} before it can be |
| 2313 // moved into a general 8-bit register. |
| 2314 auto *T_AhRcvr = makeReg(Ty); |
| 2315 T_AhRcvr->setRegClass(RCX86_IsAhRcvr); |
| 2316 _mov(T_AhRcvr, T_edx); |
| 2317 T_edx = T_AhRcvr; |
| 2318 } |
2311 _mov(Dest, T_edx); | 2319 _mov(Dest, T_edx); |
2312 } break; | 2320 } break; |
2313 case InstArithmetic::Srem: { | 2321 case InstArithmetic::Srem: { |
2314 // TODO(stichnot): Enable this after doing better performance and cross | 2322 // TODO(stichnot): Enable this after doing better performance and cross |
2315 // testing. | 2323 // testing. |
2316 if (false && Func->getOptLevel() >= Opt_1) { | 2324 if (false && Func->getOptLevel() >= Opt_1) { |
2317 // Optimize mod by constant power of 2, but not for Om1 or O0, just to | 2325 // Optimize mod by constant power of 2, but not for Om1 or O0, just to |
2318 // keep things simple there. | 2326 // keep things simple there. |
2319 if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) { | 2327 if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) { |
2320 const int32_t Divisor = C->getValue(); | 2328 const int32_t Divisor = C->getValue(); |
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2370 break; | 2378 break; |
2371 case IceType_i8: | 2379 case IceType_i8: |
2372 Eax = Traits::RegisterSet::Reg_al; | 2380 Eax = Traits::RegisterSet::Reg_al; |
2373 Edx = Traits::RegisterSet::Reg_ah; | 2381 Edx = Traits::RegisterSet::Reg_ah; |
2374 break; | 2382 break; |
2375 } | 2383 } |
2376 T_edx = makeReg(Ty, Edx); | 2384 T_edx = makeReg(Ty, Edx); |
2377 _mov(T, Src0, Eax); | 2385 _mov(T, Src0, Eax); |
2378 _cbwdq(T_edx, T); | 2386 _cbwdq(T_edx, T); |
2379 _idiv(T_edx, Src1, T); | 2387 _idiv(T_edx, Src1, T); |
| 2388 if (Ty == IceType_i8) { |
| 2389 // Register ah must be moved into one of {al,bl,cl,dl} before it can be |
| 2390 // moved into a general 8-bit register. |
| 2391 auto *T_AhRcvr = makeReg(Ty); |
| 2392 T_AhRcvr->setRegClass(RCX86_IsAhRcvr); |
| 2393 _mov(T_AhRcvr, T_edx); |
| 2394 T_edx = T_AhRcvr; |
| 2395 } |
2380 _mov(Dest, T_edx); | 2396 _mov(Dest, T_edx); |
2381 } break; | 2397 } break; |
2382 case InstArithmetic::Fadd: | 2398 case InstArithmetic::Fadd: |
2383 _mov(T, Src0); | 2399 _mov(T, Src0); |
2384 _addss(T, Src1); | 2400 _addss(T, Src1); |
2385 _mov(Dest, T); | 2401 _mov(Dest, T); |
2386 break; | 2402 break; |
2387 case InstArithmetic::Fsub: | 2403 case InstArithmetic::Fsub: |
2388 _mov(T, Src0); | 2404 _mov(T, Src0); |
2389 _subss(T, Src1); | 2405 _subss(T, Src1); |
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7423 emitGlobal(*Var, SectionSuffix); | 7439 emitGlobal(*Var, SectionSuffix); |
7424 } | 7440 } |
7425 } | 7441 } |
7426 } break; | 7442 } break; |
7427 } | 7443 } |
7428 } | 7444 } |
7429 } // end of namespace X86NAMESPACE | 7445 } // end of namespace X86NAMESPACE |
7430 } // end of namespace Ice | 7446 } // end of namespace Ice |
7431 | 7447 |
7432 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H | 7448 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H |
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