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Side by Side Diff: unittest/AssemblerX8632/XmmArith.cpp

Issue 1909013002: Subzero. X86. Lowers shufflevector using xmm instructions. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 4 years, 8 months ago
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« src/IceTargetLoweringX86BaseImpl.h ('K') | « tests_lit/llvm2ice_tests/vector-shuffle.ll ('k') | unittest/AssemblerX8664/XmmArith.cpp » ('j') | no next file with comments »
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1 //===- subzero/unittest/AssemblerX8632/XmmArith.cpp -----------------------===// 1 //===- subzero/unittest/AssemblerX8632/XmmArith.cpp -----------------------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 #include "AssemblerX8632/TestUtil.h" 9 #include "AssemblerX8632/TestUtil.h"
10 10
(...skipping 977 matching lines...) Expand 10 before | Expand all | Expand 10 after
988 \ 988 \
989 AssembledTest test = assemble(); \ 989 AssembledTest test = assemble(); \
990 test.setDqwordTo(T0, V0); \ 990 test.setDqwordTo(T0, V0); \
991 test.setDqwordTo(T1, V1); \ 991 test.setDqwordTo(T1, V1); \
992 test.run(); \ 992 test.run(); \
993 \ 993 \
994 ASSERT_EQ(Inst##Expected, test.Dst<Dqword>()) << TestString; \ 994 ASSERT_EQ(Inst##Expected, test.Dst<Dqword>()) << TestString; \
995 reset(); \ 995 reset(); \
996 } while (0) 996 } while (0)
997 997
998 #define TestImplSingleXmmXmmUntyped(Dst, Src, Inst) \
999 do { \
1000 static constexpr char TestString[] = \
1001 "(" #Dst ", " #Src ", " #Inst ", Untyped)"; \
1002 const uint32_t T0 = allocateDqword(); \
1003 const uint32_t T1 = allocateDqword(); \
1004 \
1005 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
1006 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \
1007 __ Inst(XmmRegister::Encoded_Reg_##Dst, XmmRegister::Encoded_Reg_##Src, \
1008 Immediate(Inst##Imm)); \
1009 \
1010 AssembledTest test = assemble(); \
1011 test.setDqwordTo(T0, V0); \
1012 test.setDqwordTo(T1, V1); \
1013 test.run(); \
1014 \
1015 ASSERT_EQ(Inst##UntypedExpected, test.Dst<Dqword>()) << TestString; \
1016 reset(); \
1017 } while (0)
1018
1019 #define TestImpl(Dst, Src) \ 998 #define TestImpl(Dst, Src) \
1020 do { \ 999 do { \
1021 TestImplSingleXmmXmm(Dst, Src, pshufd); \ 1000 TestImplSingleXmmXmm(Dst, Src, pshufd); \
1022 TestImplSingleXmmAddr(Dst, pshufd); \ 1001 TestImplSingleXmmAddr(Dst, pshufd); \
1023 TestImplSingleXmmXmm(Dst, Src, shufps); \ 1002 TestImplSingleXmmXmm(Dst, Src, shufps); \
1024 TestImplSingleXmmAddr(Dst, shufps); \ 1003 TestImplSingleXmmAddr(Dst, shufps); \
1025 } while (0) 1004 } while (0)
1026 1005
1027 TestImpl(xmm0, xmm1); 1006 TestImpl(xmm0, xmm1);
1007 TestImpl(xmm1, xmm2);
1008 TestImpl(xmm2, xmm3);
1009 TestImpl(xmm3, xmm4);
1010 TestImpl(xmm4, xmm5);
1011 TestImpl(xmm5, xmm6);
1012 TestImpl(xmm6, xmm7);
1013 TestImpl(xmm7, xmm0);
1014
1015 #undef TestImpl
1016 #undef TestImplSingleXmmAddr
1017 #undef TestImplSingleXmmXmm
1018 }
1019
1020 TEST_F(AssemblerX8632Test, Punpckldq) {
1021 const Dqword V0(uint64_t(0x1111111122222222ull),
1022 uint64_t(0x5555555577777777ull));
1023 const Dqword V1(uint64_t(0xAAAAAAAABBBBBBBBull),
1024 uint64_t(0xCCCCCCCCDDDDDDDDull));
1025
1026 const Dqword Expected(uint64_t(0xBBBBBBBB22222222ull),
1027 uint64_t(0xAAAAAAAA11111111ull));
1028
1029 #define TestImplXmmXmm(Dst, Src, Inst) \
1030 do { \
1031 static constexpr char TestString[] = "(" #Dst ", " #Src ", " #Inst ")"; \
1032 const uint32_t T0 = allocateDqword(); \
1033 const uint32_t T1 = allocateDqword(); \
1034 \
1035 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
1036 __ movups(XmmRegister::Encoded_Reg_##Src, dwordAddress(T1)); \
1037 __ Inst(IceType_void, XmmRegister::Encoded_Reg_##Dst, \
1038 XmmRegister::Encoded_Reg_##Src); \
1039 \
1040 AssembledTest test = assemble(); \
1041 test.setDqwordTo(T0, V0); \
1042 test.setDqwordTo(T1, V1); \
1043 test.run(); \
1044 \
1045 ASSERT_EQ(Expected, test.Dst<Dqword>()) << TestString; \
1046 reset(); \
1047 } while (0)
1048
1049 #define TestImplXmmAddr(Dst, Inst) \
1050 do { \
1051 static constexpr char TestString[] = "(" #Dst ", Addr, " #Inst ")"; \
1052 const uint32_t T0 = allocateDqword(); \
1053 const uint32_t T1 = allocateDqword(); \
1054 \
1055 __ movups(XmmRegister::Encoded_Reg_##Dst, dwordAddress(T0)); \
1056 __ Inst(IceType_void, XmmRegister::Encoded_Reg_##Dst, dwordAddress(T1)); \
1057 \
1058 AssembledTest test = assemble(); \
1059 test.setDqwordTo(T0, V0); \
1060 test.setDqwordTo(T1, V1); \
1061 test.run(); \
1062 \
1063 ASSERT_EQ(Expected, test.Dst<Dqword>()) << TestString; \
1064 reset(); \
1065 } while (0)
1066
1067 #define TestImpl(Dst, Src) \
1068 do { \
1069 TestImplXmmXmm(Dst, Src, punpckldq); \
1070 TestImplXmmAddr(Dst, punpckldq); \
1071 } while (0)
1072
1073 TestImpl(xmm0, xmm1);
1028 TestImpl(xmm1, xmm2); 1074 TestImpl(xmm1, xmm2);
1029 TestImpl(xmm2, xmm3); 1075 TestImpl(xmm2, xmm3);
1030 TestImpl(xmm3, xmm4); 1076 TestImpl(xmm3, xmm4);
1031 TestImpl(xmm4, xmm5); 1077 TestImpl(xmm4, xmm5);
1032 TestImpl(xmm5, xmm6); 1078 TestImpl(xmm5, xmm6);
1033 TestImpl(xmm6, xmm7); 1079 TestImpl(xmm6, xmm7);
1034 TestImpl(xmm7, xmm0); 1080 TestImpl(xmm7, xmm0);
1035 1081
1036 #undef TestImpl 1082 #undef TestImpl
1037 #undef TestImplSingleXmmXmmUntyped 1083 #undef TestImplXmmAddr
1038 #undef TestImplSingleXmmAddr 1084 #undef TestImplXmmXmm
1039 #undef TestImplSingleXmmXmm
1040 } 1085 }
1041 1086
1042 TEST_F(AssemblerX8632Test, Cvt) { 1087 TEST_F(AssemblerX8632Test, Cvt) {
1043 const Dqword dq2ps32DstValue(-1.0f, -1.0f, -1.0f, -1.0f); 1088 const Dqword dq2ps32DstValue(-1.0f, -1.0f, -1.0f, -1.0f);
1044 const Dqword dq2ps32SrcValue(-5, 3, 100, 200); 1089 const Dqword dq2ps32SrcValue(-5, 3, 100, 200);
1045 const Dqword dq2ps32Expected(-5.0f, 3.0f, 100.0, 200.0); 1090 const Dqword dq2ps32Expected(-5.0f, 3.0f, 100.0, 200.0);
1046 1091
1047 const Dqword dq2ps64DstValue(0.0f, 0.0f, -1.0f, -1.0f); 1092 const Dqword dq2ps64DstValue(0.0f, 0.0f, -1.0f, -1.0f);
1048 const Dqword dq2ps64SrcValue(-5, 3, 100, 200); 1093 const Dqword dq2ps64SrcValue(-5, 3, 100, 200);
1049 const Dqword dq2ps64Expected(-5.0f, 3.0f, 100.0, 200.0); 1094 const Dqword dq2ps64Expected(-5.0f, 3.0f, 100.0, 200.0);
(...skipping 795 matching lines...) Expand 10 before | Expand all | Expand 10 after
1845 TestImpl(xmm6, ebx, 7); 1890 TestImpl(xmm6, ebx, 7);
1846 TestImpl(xmm7, ecx, 8); 1891 TestImpl(xmm7, ecx, 8);
1847 1892
1848 #undef TestImpl 1893 #undef TestImpl
1849 } 1894 }
1850 1895
1851 } // end of anonymous namespace 1896 } // end of anonymous namespace
1852 } // end of namespace Test 1897 } // end of namespace Test
1853 } // end of namespace X8632 1898 } // end of namespace X8632
1854 } // end of namespace Ice 1899 } // end of namespace Ice
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« src/IceTargetLoweringX86BaseImpl.h ('K') | « tests_lit/llvm2ice_tests/vector-shuffle.ll ('k') | unittest/AssemblerX8664/XmmArith.cpp » ('j') | no next file with comments »

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