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Side by Side Diff: tests_lit/llvm2ice_tests/bool-folding.ll

Issue 1904233002: Subzero: Fix over-aggressive bool folding. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Hack for pure virtual method Created 4 years, 8 months ago
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1 ; This tests the optimization where producers and consumers of i1 (bool) 1 ; This tests the optimization where producers and consumers of i1 (bool)
2 ; variables are combined to implicitly use flags instead of explicitly using 2 ; variables are combined to implicitly use flags instead of explicitly using
3 ; stack or register variables. 3 ; stack or register variables.
4 4
5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
6 ; RUN: -allow-externally-defined-symbols | FileCheck %s 6 ; RUN: -allow-externally-defined-symbols | FileCheck %s
7 7
8 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ 8 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
9 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ 9 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \
10 ; RUN: -allow-externally-defined-symbols \ 10 ; RUN: -allow-externally-defined-symbols \
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262 ; ARM32: mov 262 ; ARM32: mov
263 ; ARM32: tst 263 ; ARM32: tst
264 ; ARM32: movne 264 ; ARM32: movne
265 ; ARM32: mov 265 ; ARM32: mov
266 ; ARM32: tst 266 ; ARM32: tst
267 ; ARM32: movne 267 ; ARM32: movne
268 ; ARM32: tst 268 ; ARM32: tst
269 ; ARM32: movne 269 ; ARM32: movne
270 ; ARM32: bx lr 270 ; ARM32: bx lr
271 271
272 ; Cmp/branch non-folding due to load folding and intervening store.
273 define internal i32 @no_fold_cmp_br_store(i32 %arg2, i32 %argaddr) {
274 entry:
275 %addr = inttoptr i32 %argaddr to i32*
276 %arg1 = load i32, i32* %addr, align 1
277 %cmp1 = icmp slt i32 %arg1, %arg2
278 store i32 1, i32* %addr, align 1
279 br i1 %cmp1, label %branch1, label %branch2
280 branch1:
281 ret i32 1
282 branch2:
283 ret i32 2
284 }
285
286 ; CHECK-LABEL: no_fold_cmp_br_store
287 ; CHECK: cmp
288 ; CHECK: set
289 ; CHECK: cmp
290
291 ; Cmp/select non-folding due to load folding and intervening store.
292 define internal i32 @no_fold_cmp_select_store(i32 %arg1, i32 %argaddr) {
293 entry:
294 %addr = inttoptr i32 %argaddr to i32*
295 %arg2 = load i32, i32* %addr, align 1
296 %cmp1 = icmp slt i32 %arg1, %arg2
297 store i32 1, i32* %addr, align 1
298 %result = select i1 %cmp1, i32 %arg1, i32 %argaddr
299 ret i32 %result
300 }
301
302 ; CHECK-LABEL: no_fold_cmp_select_store
303 ; CHECK: cmp
304 ; CHECK: setl
305 ; CHECK: mov DWORD PTR
306 ; CHECK: cmp
307 ; CHECK: cmovne
308
309 ; Cmp/select folding due to load folding and non-intervening store.
310 define internal i32 @fold_cmp_select_store(i32 %arg1, i32 %argaddr) {
311 entry:
312 %addr = inttoptr i32 %argaddr to i32*
313 %arg2 = load i32, i32* %addr, align 1
314 %cmp1 = icmp slt i32 %arg1, %arg2
315 %result = select i1 %cmp1, i32 %arg1, i32 %argaddr
316 store i32 1, i32* %addr, align 1
317 ret i32 %result
318 }
319
320 ; CHECK-LABEL: fold_cmp_select_store
321 ; CHECK: cmp {{.*}},DWORD PTR
322 ; CHECK: cmovl
323
272 ; Cmp/multi-select non-folding because of extra non-whitelisted uses. 324 ; Cmp/multi-select non-folding because of extra non-whitelisted uses.
273 define internal i32 @no_fold_cmp_select_multi_non_whitelist(i32 %arg1, 325 define internal i32 @no_fold_cmp_select_multi_non_whitelist(i32 %arg1,
274 i32 %arg2) { 326 i32 %arg2) {
275 entry: 327 entry:
276 %cmp1 = icmp slt i32 %arg1, %arg2 328 %cmp1 = icmp slt i32 %arg1, %arg2
277 %a = select i1 %cmp1, i32 %arg1, i32 %arg2 329 %a = select i1 %cmp1, i32 %arg1, i32 %arg2
278 %b = select i1 %cmp1, i32 %arg2, i32 %arg1 330 %b = select i1 %cmp1, i32 %arg2, i32 %arg1
279 %c = select i1 %cmp1, i32 123, i32 %arg1 331 %c = select i1 %cmp1, i32 123, i32 %arg1
280 %ext = zext i1 %cmp1 to i32 332 %ext = zext i1 %cmp1 to i32
281 %partial1 = add i32 %a, %b 333 %partial1 = add i32 %a, %b
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420 ; ARM32: tst r0, #1 472 ; ARM32: tst r0, #1
421 ; ARM32: bne 473 ; ARM32: bne
422 ; ARM32: tst r1, #1 474 ; ARM32: tst r1, #1
423 ; ARM32: beq 475 ; ARM32: beq
424 ; ARM32: tst r2, #1 476 ; ARM32: tst r2, #1
425 ; ARM32: bne {{.*}}target_true 477 ; ARM32: bne {{.*}}target_true
426 ; ARM32: tst r3, #1 478 ; ARM32: tst r3, #1
427 ; ARM32: beq {{.*}}target_false 479 ; ARM32: beq {{.*}}target_false
428 ; ARM32: tst r4, #1 480 ; ARM32: tst r4, #1
429 ; ARM32: beq {{.*}}target_false 481 ; ARM32: beq {{.*}}target_false
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