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Side by Side Diff: src/IceIntrinsics.cpp

Issue 1904233002: Subzero: Fix over-aggressive bool folding. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Hack for pure virtual method Created 4 years, 8 months ago
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1 //===- subzero/src/IceIntrinsics.cpp - Functions related to intrinsics ----===// 1 //===- subzero/src/IceIntrinsics.cpp - Functions related to intrinsics ----===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
(...skipping 13 matching lines...) Expand all
24 24
25 #include <utility> 25 #include <utility>
26 26
27 namespace Ice { 27 namespace Ice {
28 28
29 static_assert(sizeof(Intrinsics::IntrinsicInfo) == 4, 29 static_assert(sizeof(Intrinsics::IntrinsicInfo) == 4,
30 "Unexpected sizeof(IntrinsicInfo)"); 30 "Unexpected sizeof(IntrinsicInfo)");
31 31
32 namespace { 32 namespace {
33 33
34 #define INTRIN(ID, SE, RT) \ 34 #define INTRIN(ID, SE, RT, MW) \
35 { Intrinsics::ID, Intrinsics::SE, Intrinsics::RT } 35 { Intrinsics::ID, Intrinsics::SE, Intrinsics::RT, Intrinsics::MW }
36 36
37 // Build list of intrinsics with their attributes and expected prototypes. List 37 // Build list of intrinsics with their attributes and expected prototypes. List
38 // is sorted alphabetically. 38 // is sorted alphabetically.
39 const struct IceIntrinsicsEntry_ { 39 const struct IceIntrinsicsEntry_ {
40 Intrinsics::FullIntrinsicInfo Info; 40 Intrinsics::FullIntrinsicInfo Info;
41 const char *IntrinsicName; 41 const char *IntrinsicName;
42 } IceIntrinsicsTable[] = { 42 } IceIntrinsicsTable[] = {
43 43
44 #define AtomicCmpxchgInit(Overload, NameSuffix) \ 44 #define AtomicCmpxchgInit(Overload, NameSuffix) \
45 { \ 45 { \
46 { \ 46 { \
47 INTRIN(AtomicCmpxchg, SideEffects_T, ReturnsTwice_F), {Overload, \ 47 INTRIN(AtomicCmpxchg, SideEffects_T, ReturnsTwice_F, MemoryWrite_T), \
48 IceType_i32, \ 48 {Overload, IceType_i32, Overload, Overload, IceType_i32, IceType_i32}, \
49 Overload, \ 49 6 \
50 Overload, \ 50 } \
51 IceType_i32, \ 51 , "llvm.nacl.atomic.cmpxchg." NameSuffix \
52 IceType_i32}, \
53 6 \
54 } \
55 , "llvm.nacl.atomic.cmpxchg." NameSuffix \
56 } 52 }
57 AtomicCmpxchgInit(IceType_i8, "i8"), 53 AtomicCmpxchgInit(IceType_i8, "i8"),
58 AtomicCmpxchgInit(IceType_i16, "i16"), 54 AtomicCmpxchgInit(IceType_i16, "i16"),
59 AtomicCmpxchgInit(IceType_i32, "i32"), 55 AtomicCmpxchgInit(IceType_i32, "i32"),
60 AtomicCmpxchgInit(IceType_i64, "i64"), 56 AtomicCmpxchgInit(IceType_i64, "i64"),
61 #undef AtomicCmpxchgInit 57 #undef AtomicCmpxchgInit
62 58
63 {{INTRIN(AtomicFence, SideEffects_T, ReturnsTwice_F), 59 {{INTRIN(AtomicFence, SideEffects_T, ReturnsTwice_F, MemoryWrite_T),
64 {IceType_void, IceType_i32}, 60 {IceType_void, IceType_i32},
65 2}, 61 2},
66 "llvm.nacl.atomic.fence"}, 62 "llvm.nacl.atomic.fence"},
67 {{INTRIN(AtomicFenceAll, SideEffects_T, ReturnsTwice_F), {IceType_void}, 1}, 63 {{INTRIN(AtomicFenceAll, SideEffects_T, ReturnsTwice_F, MemoryWrite_T),
64 {IceType_void},
65 1},
68 "llvm.nacl.atomic.fence.all"}, 66 "llvm.nacl.atomic.fence.all"},
69 {{INTRIN(AtomicIsLockFree, SideEffects_F, ReturnsTwice_F), 67 {{INTRIN(AtomicIsLockFree, SideEffects_F, ReturnsTwice_F, MemoryWrite_F),
70 {IceType_i1, IceType_i32, IceType_i32}, 68 {IceType_i1, IceType_i32, IceType_i32},
71 3}, 69 3},
72 "llvm.nacl.atomic.is.lock.free"}, 70 "llvm.nacl.atomic.is.lock.free"},
73 71
74 #define AtomicLoadInit(Overload, NameSuffix) \ 72 #define AtomicLoadInit(Overload, NameSuffix) \
75 { \ 73 { \
76 { \ 74 { \
77 INTRIN(AtomicLoad, SideEffects_T, ReturnsTwice_F), \ 75 INTRIN(AtomicLoad, SideEffects_T, ReturnsTwice_F, MemoryWrite_T), \
78 {Overload, IceType_i32, IceType_i32}, 3 \ 76 {Overload, IceType_i32, IceType_i32}, 3 \
79 } \ 77 } \
80 , "llvm.nacl.atomic.load." NameSuffix \ 78 , "llvm.nacl.atomic.load." NameSuffix \
81 } 79 }
82 AtomicLoadInit(IceType_i8, "i8"), 80 AtomicLoadInit(IceType_i8, "i8"),
83 AtomicLoadInit(IceType_i16, "i16"), 81 AtomicLoadInit(IceType_i16, "i16"),
84 AtomicLoadInit(IceType_i32, "i32"), 82 AtomicLoadInit(IceType_i32, "i32"),
85 AtomicLoadInit(IceType_i64, "i64"), 83 AtomicLoadInit(IceType_i64, "i64"),
86 #undef AtomicLoadInit 84 #undef AtomicLoadInit
87 85
88 #define AtomicRMWInit(Overload, NameSuffix) \ 86 #define AtomicRMWInit(Overload, NameSuffix) \
89 { \ 87 { \
90 { \ 88 { \
91 INTRIN(AtomicRMW, SideEffects_T, ReturnsTwice_F) \ 89 INTRIN(AtomicRMW, SideEffects_T, ReturnsTwice_F, MemoryWrite_T) \
92 , {Overload, IceType_i32, IceType_i32, Overload, IceType_i32}, 5 \ 90 , {Overload, IceType_i32, IceType_i32, Overload, IceType_i32}, 5 \
93 } \ 91 } \
94 , "llvm.nacl.atomic.rmw." NameSuffix \ 92 , "llvm.nacl.atomic.rmw." NameSuffix \
95 } 93 }
96 AtomicRMWInit(IceType_i8, "i8"), 94 AtomicRMWInit(IceType_i8, "i8"),
97 AtomicRMWInit(IceType_i16, "i16"), 95 AtomicRMWInit(IceType_i16, "i16"),
98 AtomicRMWInit(IceType_i32, "i32"), 96 AtomicRMWInit(IceType_i32, "i32"),
99 AtomicRMWInit(IceType_i64, "i64"), 97 AtomicRMWInit(IceType_i64, "i64"),
100 #undef AtomicRMWInit 98 #undef AtomicRMWInit
101 99
102 #define AtomicStoreInit(Overload, NameSuffix) \ 100 #define AtomicStoreInit(Overload, NameSuffix) \
103 { \ 101 { \
104 { \ 102 { \
105 INTRIN(AtomicStore, SideEffects_T, ReturnsTwice_F) \ 103 INTRIN(AtomicStore, SideEffects_T, ReturnsTwice_F, MemoryWrite_T) \
106 , {IceType_void, Overload, IceType_i32, IceType_i32}, 4 \ 104 , {IceType_void, Overload, IceType_i32, IceType_i32}, 4 \
107 } \ 105 } \
108 , "llvm.nacl.atomic.store." NameSuffix \ 106 , "llvm.nacl.atomic.store." NameSuffix \
109 } 107 }
110 AtomicStoreInit(IceType_i8, "i8"), 108 AtomicStoreInit(IceType_i8, "i8"),
111 AtomicStoreInit(IceType_i16, "i16"), 109 AtomicStoreInit(IceType_i16, "i16"),
112 AtomicStoreInit(IceType_i32, "i32"), 110 AtomicStoreInit(IceType_i32, "i32"),
113 AtomicStoreInit(IceType_i64, "i64"), 111 AtomicStoreInit(IceType_i64, "i64"),
114 #undef AtomicStoreInit 112 #undef AtomicStoreInit
115 113
116 #define BswapInit(Overload, NameSuffix) \ 114 #define BswapInit(Overload, NameSuffix) \
117 { \ 115 { \
118 { \ 116 { \
119 INTRIN(Bswap, SideEffects_F, ReturnsTwice_F) \ 117 INTRIN(Bswap, SideEffects_F, ReturnsTwice_F, MemoryWrite_F) \
120 , {Overload, Overload}, 2 \ 118 , {Overload, Overload}, 2 \
121 } \ 119 } \
122 , "llvm.bswap." NameSuffix \ 120 , "llvm.bswap." NameSuffix \
123 } 121 }
124 BswapInit(IceType_i16, "i16"), 122 BswapInit(IceType_i16, "i16"),
125 BswapInit(IceType_i32, "i32"), 123 BswapInit(IceType_i32, "i32"),
126 BswapInit(IceType_i64, "i64"), 124 BswapInit(IceType_i64, "i64"),
127 #undef BswapInit 125 #undef BswapInit
128 126
129 #define CtlzInit(Overload, NameSuffix) \ 127 #define CtlzInit(Overload, NameSuffix) \
130 { \ 128 { \
131 { \ 129 { \
132 INTRIN(Ctlz, SideEffects_F, ReturnsTwice_F) \ 130 INTRIN(Ctlz, SideEffects_F, ReturnsTwice_F, MemoryWrite_F) \
133 , {Overload, Overload, IceType_i1}, 3 \ 131 , {Overload, Overload, IceType_i1}, 3 \
134 } \ 132 } \
135 , "llvm.ctlz." NameSuffix \ 133 , "llvm.ctlz." NameSuffix \
136 } 134 }
137 CtlzInit(IceType_i32, "i32"), 135 CtlzInit(IceType_i32, "i32"),
138 CtlzInit(IceType_i64, "i64"), 136 CtlzInit(IceType_i64, "i64"),
139 #undef CtlzInit 137 #undef CtlzInit
140 138
141 #define CtpopInit(Overload, NameSuffix) \ 139 #define CtpopInit(Overload, NameSuffix) \
142 { \ 140 { \
143 { \ 141 { \
144 INTRIN(Ctpop, SideEffects_F, ReturnsTwice_F) \ 142 INTRIN(Ctpop, SideEffects_F, ReturnsTwice_F, MemoryWrite_F) \
145 , {Overload, Overload}, 2 \ 143 , {Overload, Overload}, 2 \
146 } \ 144 } \
147 , "llvm.ctpop." NameSuffix \ 145 , "llvm.ctpop." NameSuffix \
148 } 146 }
149 CtpopInit(IceType_i32, "i32"), 147 CtpopInit(IceType_i32, "i32"),
150 CtpopInit(IceType_i64, "i64"), 148 CtpopInit(IceType_i64, "i64"),
151 #undef CtpopInit 149 #undef CtpopInit
152 150
153 #define CttzInit(Overload, NameSuffix) \ 151 #define CttzInit(Overload, NameSuffix) \
154 { \ 152 { \
155 { \ 153 { \
156 INTRIN(Cttz, SideEffects_F, ReturnsTwice_F) \ 154 INTRIN(Cttz, SideEffects_F, ReturnsTwice_F, MemoryWrite_F) \
157 , {Overload, Overload, IceType_i1}, 3 \ 155 , {Overload, Overload, IceType_i1}, 3 \
158 } \ 156 } \
159 , "llvm.cttz." NameSuffix \ 157 , "llvm.cttz." NameSuffix \
160 } 158 }
161 CttzInit(IceType_i32, "i32"), 159 CttzInit(IceType_i32, "i32"),
162 CttzInit(IceType_i64, "i64"), 160 CttzInit(IceType_i64, "i64"),
163 #undef CttzInit 161 #undef CttzInit
164 162
165 #define FabsInit(Overload, NameSuffix) \ 163 #define FabsInit(Overload, NameSuffix) \
166 { \ 164 { \
167 { INTRIN(Fabs, SideEffects_F, ReturnsTwice_F), {Overload, Overload}, 2 } \ 165 { \
166 INTRIN(Fabs, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
167 {Overload, Overload}, 2 \
168 } \
168 , "llvm.fabs." NameSuffix \ 169 , "llvm.fabs." NameSuffix \
169 } 170 }
170 FabsInit(IceType_f32, "f32"), 171 FabsInit(IceType_f32, "f32"),
171 FabsInit(IceType_f64, "f64"), 172 FabsInit(IceType_f64, "f64"),
172 FabsInit(IceType_v4f32, "v4f32"), 173 FabsInit(IceType_v4f32, "v4f32"),
173 #undef FabsInit 174 #undef FabsInit
174 175
175 {{INTRIN(Longjmp, SideEffects_T, ReturnsTwice_F), 176 {{INTRIN(Longjmp, SideEffects_T, ReturnsTwice_F, MemoryWrite_F),
176 {IceType_void, IceType_i32, IceType_i32}, 177 {IceType_void, IceType_i32, IceType_i32},
177 3}, 178 3},
178 "llvm.nacl.longjmp"}, 179 "llvm.nacl.longjmp"},
179 {{INTRIN(Memcpy, SideEffects_T, ReturnsTwice_F), 180 {{INTRIN(Memcpy, SideEffects_T, ReturnsTwice_F, MemoryWrite_T),
180 {IceType_void, IceType_i32, IceType_i32, IceType_i32, IceType_i32, 181 {IceType_void, IceType_i32, IceType_i32, IceType_i32, IceType_i32,
181 IceType_i1}, 182 IceType_i1},
182 6}, 183 6},
183 "llvm.memcpy.p0i8.p0i8.i32"}, 184 "llvm.memcpy.p0i8.p0i8.i32"},
184 {{INTRIN(Memmove, SideEffects_T, ReturnsTwice_F), 185 {{INTRIN(Memmove, SideEffects_T, ReturnsTwice_F, MemoryWrite_T),
185 {IceType_void, IceType_i32, IceType_i32, IceType_i32, IceType_i32, 186 {IceType_void, IceType_i32, IceType_i32, IceType_i32, IceType_i32,
186 IceType_i1}, 187 IceType_i1},
187 6}, 188 6},
188 "llvm.memmove.p0i8.p0i8.i32"}, 189 "llvm.memmove.p0i8.p0i8.i32"},
189 {{INTRIN(Memset, SideEffects_T, ReturnsTwice_F), 190 {{INTRIN(Memset, SideEffects_T, ReturnsTwice_F, MemoryWrite_T),
190 {IceType_void, IceType_i32, IceType_i8, IceType_i32, IceType_i32, 191 {IceType_void, IceType_i32, IceType_i8, IceType_i32, IceType_i32,
191 IceType_i1}, 192 IceType_i1},
192 6}, 193 6},
193 "llvm.memset.p0i8.i32"}, 194 "llvm.memset.p0i8.i32"},
194 {{INTRIN(NaClReadTP, SideEffects_F, ReturnsTwice_F), {IceType_i32}, 1}, 195 {{INTRIN(NaClReadTP, SideEffects_F, ReturnsTwice_F, MemoryWrite_F),
196 {IceType_i32},
197 1},
195 "llvm.nacl.read.tp"}, 198 "llvm.nacl.read.tp"},
196 {{INTRIN(Setjmp, SideEffects_T, ReturnsTwice_T), 199 {{INTRIN(Setjmp, SideEffects_T, ReturnsTwice_T, MemoryWrite_T),
197 {IceType_i32, IceType_i32}, 200 {IceType_i32, IceType_i32},
198 2}, 201 2},
199 "llvm.nacl.setjmp"}, 202 "llvm.nacl.setjmp"},
200 203
201 #define SqrtInit(Overload, NameSuffix) \ 204 #define SqrtInit(Overload, NameSuffix) \
202 { \ 205 { \
203 { INTRIN(Sqrt, SideEffects_F, ReturnsTwice_F), {Overload, Overload}, 2 } \ 206 { \
207 INTRIN(Sqrt, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
208 {Overload, Overload}, 2 \
209 } \
204 , "llvm.sqrt." NameSuffix \ 210 , "llvm.sqrt." NameSuffix \
205 } 211 }
206 SqrtInit(IceType_f32, "f32"), 212 SqrtInit(IceType_f32, "f32"),
207 SqrtInit(IceType_f64, "f64"), 213 SqrtInit(IceType_f64, "f64"),
208 #undef SqrtInit 214 #undef SqrtInit
209 215
210 {{INTRIN(Stacksave, SideEffects_T, ReturnsTwice_F), {IceType_i32}, 1}, 216 {{INTRIN(Stacksave, SideEffects_T, ReturnsTwice_F, MemoryWrite_F),
217 {IceType_i32},
218 1},
211 "llvm.stacksave"}, 219 "llvm.stacksave"},
212 {{INTRIN(Stackrestore, SideEffects_T, ReturnsTwice_F), 220 {{INTRIN(Stackrestore, SideEffects_T, ReturnsTwice_F, MemoryWrite_F),
213 {IceType_void, IceType_i32}, 221 {IceType_void, IceType_i32},
214 2}, 222 2},
215 "llvm.stackrestore"}, 223 "llvm.stackrestore"},
216 {{INTRIN(Trap, SideEffects_T, ReturnsTwice_F), {IceType_void}, 1}, 224 {{INTRIN(Trap, SideEffects_T, ReturnsTwice_F, MemoryWrite_F),
225 {IceType_void},
226 1},
217 "llvm.trap"}}; 227 "llvm.trap"}};
218 const size_t IceIntrinsicsTableSize = llvm::array_lengthof(IceIntrinsicsTable); 228 const size_t IceIntrinsicsTableSize = llvm::array_lengthof(IceIntrinsicsTable);
219 229
220 #undef INTRIN 230 #undef INTRIN
221 231
222 } // end of anonymous namespace 232 } // end of anonymous namespace
223 233
224 Intrinsics::Intrinsics(GlobalContext *Ctx) { 234 Intrinsics::Intrinsics(GlobalContext *Ctx) {
225 for (size_t I = 0; I < IceIntrinsicsTableSize; ++I) { 235 for (size_t I = 0; I < IceIntrinsicsTableSize; ++I) {
226 const struct IceIntrinsicsEntry_ &Entry = IceIntrinsicsTable[I]; 236 const struct IceIntrinsicsEntry_ &Entry = IceIntrinsicsTable[I];
(...skipping 110 matching lines...) Expand 10 before | Expand all | Expand 10 after
337 return Intrinsics::IsValidCall; 347 return Intrinsics::IsValidCall;
338 } 348 }
339 349
340 Type Intrinsics::FullIntrinsicInfo::getArgType(SizeT Index) const { 350 Type Intrinsics::FullIntrinsicInfo::getArgType(SizeT Index) const {
341 assert(NumTypes > 1); 351 assert(NumTypes > 1);
342 assert(Index + 1 < NumTypes); 352 assert(Index + 1 < NumTypes);
343 return Signature[Index + 1]; 353 return Signature[Index + 1];
344 } 354 }
345 355
346 } // end of namespace Ice 356 } // end of namespace Ice
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