MIPS: Implement unaligned access instruction.

src/mips/assembler-mips.cc

Index: src/mips/assembler-mips.cc
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index bfa232892a941fc3f57f4b768f650cfb93997ff9..23a996aab15870b0920c87a3a479634e47deac9f 100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -1829,11 +1829,13 @@ void Assembler::lw(Register rd, const MemOperand& rs) {
 
 
 void Assembler::lwl(Register rd, const MemOperand& rs) {
+  DCHECK(is_int16(rs.offset_));

[balazs.kilvady, 2016/04/26 12:08:41]

 removed in Release 6 so please add a DCHECK().

   GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
 }
 
 
 void Assembler::lwr(Register rd, const MemOperand& rs) {
+  DCHECK(is_int16(rs.offset_));

[balazs.kilvady, 2016/04/26 12:08:41]

 removed in Release 6 so please add a DCHECK().

   GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
 }
 
@@ -1869,11 +1871,13 @@ void Assembler::sw(Register rd, const MemOperand& rs) {
 
 
 void Assembler::swl(Register rd, const MemOperand& rs) {
+  DCHECK(is_int16(rs.offset_));

[balazs.kilvady, 2016/04/26 12:08:41]

 removed in Release 6 so please add a DCHECK().

   GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
 }
 
 
 void Assembler::swr(Register rd, const MemOperand& rs) {
+  DCHECK(is_int16(rs.offset_));

[balazs.kilvady, 2016/04/26 12:08:41]

 removed in Release 6 so please add a DCHECK().

   GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
 }