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Side by Side Diff: src/mips64/macro-assembler-mips64.h

Issue 1902743002: MIPS: Implement unaligned access instruction. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Address code review remarks Created 4 years, 7 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 5 #ifndef V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 6 #define V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
7 7
8 #include "src/assembler.h" 8 #include "src/assembler.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 #include "src/mips64/assembler-mips64.h" 10 #include "src/mips64/assembler-mips64.h"
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708 Register scratch = at); 708 Register scratch = at);
709 709
710 void Pref(int32_t hint, const MemOperand& rs); 710 void Pref(int32_t hint, const MemOperand& rs);
711 711
712 712
713 // --------------------------------------------------------------------------- 713 // ---------------------------------------------------------------------------
714 // Pseudo-instructions. 714 // Pseudo-instructions.
715 715
716 void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); } 716 void mov(Register rd, Register rt) { or_(rd, rt, zero_reg); }
717 717
718 void Ulh(Register rd, const MemOperand& rs);
719 void Ulhu(Register rd, const MemOperand& rs);
720 void Ush(Register rd, const MemOperand& rs, Register scratch);
721
718 void Ulw(Register rd, const MemOperand& rs); 722 void Ulw(Register rd, const MemOperand& rs);
723 void Ulwu(Register rd, const MemOperand& rs);
719 void Usw(Register rd, const MemOperand& rs); 724 void Usw(Register rd, const MemOperand& rs);
720 void Uld(Register rd, const MemOperand& rs, Register scratch = at); 725
721 void Usd(Register rd, const MemOperand& rs, Register scratch = at); 726 void Uld(Register rd, const MemOperand& rs);
727 void Usd(Register rd, const MemOperand& rs);
728
729 void Ulwc1(FPURegister fd, const MemOperand& rs, Register scratch);
730 void Uswc1(FPURegister fd, const MemOperand& rs, Register scratch);
731
732 void Uldc1(FPURegister fd, const MemOperand& rs, Register scratch);
733 void Usdc1(FPURegister fd, const MemOperand& rs, Register scratch);
722 734
723 void LoadWordPair(Register rd, const MemOperand& rs, Register scratch = at); 735 void LoadWordPair(Register rd, const MemOperand& rs, Register scratch = at);
724 void StoreWordPair(Register rd, const MemOperand& rs, Register scratch = at); 736 void StoreWordPair(Register rd, const MemOperand& rs, Register scratch = at);
725 737
726 // Load int32 in the rd register. 738 // Load int32 in the rd register.
727 void li(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE); 739 void li(Register rd, Operand j, LiFlags mode = OPTIMIZE_SIZE);
728 inline bool LiLower32BitHelper(Register rd, Operand j); 740 inline bool LiLower32BitHelper(Register rd, Operand j);
729 inline void li(Register rd, int64_t j, LiFlags mode = OPTIMIZE_SIZE) { 741 inline void li(Register rd, int64_t j, LiFlags mode = OPTIMIZE_SIZE) {
730 li(rd, Operand(j), mode); 742 li(rd, Operand(j), mode);
731 } 743 }
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2010 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__) 2022 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
2011 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm-> 2023 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
2012 #else 2024 #else
2013 #define ACCESS_MASM(masm) masm-> 2025 #define ACCESS_MASM(masm) masm->
2014 #endif 2026 #endif
2015 2027
2016 } // namespace internal 2028 } // namespace internal
2017 } // namespace v8 2029 } // namespace v8
2018 2030
2019 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_ 2031 #endif // V8_MIPS_MACRO_ASSEMBLER_MIPS_H_
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