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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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1994 if (is_int16(rs.offset_)) { | 1994 if (is_int16(rs.offset_)) { |
1995 GenInstrImmediate(LWU, rs.rm(), rd, rs.offset_); | 1995 GenInstrImmediate(LWU, rs.rm(), rd, rs.offset_); |
1996 } else { // Offset > 16 bits, use multiple instructions to load. | 1996 } else { // Offset > 16 bits, use multiple instructions to load. |
1997 LoadRegPlusOffsetToAt(rs); | 1997 LoadRegPlusOffsetToAt(rs); |
1998 GenInstrImmediate(LWU, at, rd, 0); // Equiv to lwu(rd, MemOperand(at, 0)); | 1998 GenInstrImmediate(LWU, at, rd, 0); // Equiv to lwu(rd, MemOperand(at, 0)); |
1999 } | 1999 } |
2000 } | 2000 } |
2001 | 2001 |
2002 | 2002 |
2003 void Assembler::lwl(Register rd, const MemOperand& rs) { | 2003 void Assembler::lwl(Register rd, const MemOperand& rs) { |
| 2004 DCHECK(is_int16(rs.offset_)); |
| 2005 DCHECK(kArchVariant == kMips64r2); |
2004 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); | 2006 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); |
2005 } | 2007 } |
2006 | 2008 |
2007 | 2009 |
2008 void Assembler::lwr(Register rd, const MemOperand& rs) { | 2010 void Assembler::lwr(Register rd, const MemOperand& rs) { |
| 2011 DCHECK(is_int16(rs.offset_)); |
| 2012 DCHECK(kArchVariant == kMips64r2); |
2009 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); | 2013 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); |
2010 } | 2014 } |
2011 | 2015 |
2012 | 2016 |
2013 void Assembler::sb(Register rd, const MemOperand& rs) { | 2017 void Assembler::sb(Register rd, const MemOperand& rs) { |
2014 if (is_int16(rs.offset_)) { | 2018 if (is_int16(rs.offset_)) { |
2015 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_); | 2019 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_); |
2016 } else { // Offset > 16 bits, use multiple instructions to store. | 2020 } else { // Offset > 16 bits, use multiple instructions to store. |
2017 LoadRegPlusOffsetToAt(rs); | 2021 LoadRegPlusOffsetToAt(rs); |
2018 GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0)); | 2022 GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0)); |
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2034 if (is_int16(rs.offset_)) { | 2038 if (is_int16(rs.offset_)) { |
2035 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_); | 2039 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_); |
2036 } else { // Offset > 16 bits, use multiple instructions to store. | 2040 } else { // Offset > 16 bits, use multiple instructions to store. |
2037 LoadRegPlusOffsetToAt(rs); | 2041 LoadRegPlusOffsetToAt(rs); |
2038 GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0)); | 2042 GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0)); |
2039 } | 2043 } |
2040 } | 2044 } |
2041 | 2045 |
2042 | 2046 |
2043 void Assembler::swl(Register rd, const MemOperand& rs) { | 2047 void Assembler::swl(Register rd, const MemOperand& rs) { |
| 2048 DCHECK(is_int16(rs.offset_)); |
| 2049 DCHECK(kArchVariant == kMips64r2); |
2044 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); | 2050 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); |
2045 } | 2051 } |
2046 | 2052 |
2047 | 2053 |
2048 void Assembler::swr(Register rd, const MemOperand& rs) { | 2054 void Assembler::swr(Register rd, const MemOperand& rs) { |
| 2055 DCHECK(is_int16(rs.offset_)); |
| 2056 DCHECK(kArchVariant == kMips64r2); |
2049 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); | 2057 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); |
2050 } | 2058 } |
2051 | 2059 |
2052 | 2060 |
2053 void Assembler::lui(Register rd, int32_t j) { | 2061 void Assembler::lui(Register rd, int32_t j) { |
2054 DCHECK(is_uint16(j)); | 2062 DCHECK(is_uint16(j)); |
2055 GenInstrImmediate(LUI, zero_reg, rd, j); | 2063 GenInstrImmediate(LUI, zero_reg, rd, j); |
2056 } | 2064 } |
2057 | 2065 |
2058 | 2066 |
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2077 } | 2085 } |
2078 | 2086 |
2079 | 2087 |
2080 void Assembler::dati(Register rs, int32_t j) { | 2088 void Assembler::dati(Register rs, int32_t j) { |
2081 DCHECK(is_uint16(j)); | 2089 DCHECK(is_uint16(j)); |
2082 GenInstrImmediate(REGIMM, rs, DATI, j); | 2090 GenInstrImmediate(REGIMM, rs, DATI, j); |
2083 } | 2091 } |
2084 | 2092 |
2085 | 2093 |
2086 void Assembler::ldl(Register rd, const MemOperand& rs) { | 2094 void Assembler::ldl(Register rd, const MemOperand& rs) { |
| 2095 DCHECK(is_int16(rs.offset_)); |
| 2096 DCHECK(kArchVariant == kMips64r2); |
2087 GenInstrImmediate(LDL, rs.rm(), rd, rs.offset_); | 2097 GenInstrImmediate(LDL, rs.rm(), rd, rs.offset_); |
2088 } | 2098 } |
2089 | 2099 |
2090 | 2100 |
2091 void Assembler::ldr(Register rd, const MemOperand& rs) { | 2101 void Assembler::ldr(Register rd, const MemOperand& rs) { |
| 2102 DCHECK(is_int16(rs.offset_)); |
| 2103 DCHECK(kArchVariant == kMips64r2); |
2092 GenInstrImmediate(LDR, rs.rm(), rd, rs.offset_); | 2104 GenInstrImmediate(LDR, rs.rm(), rd, rs.offset_); |
2093 } | 2105 } |
2094 | 2106 |
2095 | 2107 |
2096 void Assembler::sdl(Register rd, const MemOperand& rs) { | 2108 void Assembler::sdl(Register rd, const MemOperand& rs) { |
| 2109 DCHECK(is_int16(rs.offset_)); |
| 2110 DCHECK(kArchVariant == kMips64r2); |
2097 GenInstrImmediate(SDL, rs.rm(), rd, rs.offset_); | 2111 GenInstrImmediate(SDL, rs.rm(), rd, rs.offset_); |
2098 } | 2112 } |
2099 | 2113 |
2100 | 2114 |
2101 void Assembler::sdr(Register rd, const MemOperand& rs) { | 2115 void Assembler::sdr(Register rd, const MemOperand& rs) { |
| 2116 DCHECK(is_int16(rs.offset_)); |
| 2117 DCHECK(kArchVariant == kMips64r2); |
2102 GenInstrImmediate(SDR, rs.rm(), rd, rs.offset_); | 2118 GenInstrImmediate(SDR, rs.rm(), rd, rs.offset_); |
2103 } | 2119 } |
2104 | 2120 |
2105 | 2121 |
2106 void Assembler::ld(Register rd, const MemOperand& rs) { | 2122 void Assembler::ld(Register rd, const MemOperand& rs) { |
2107 if (is_int16(rs.offset_)) { | 2123 if (is_int16(rs.offset_)) { |
2108 GenInstrImmediate(LD, rs.rm(), rd, rs.offset_); | 2124 GenInstrImmediate(LD, rs.rm(), rd, rs.offset_); |
2109 } else { // Offset > 16 bits, use multiple instructions to load. | 2125 } else { // Offset > 16 bits, use multiple instructions to load. |
2110 LoadRegPlusOffsetToAt(rs); | 2126 LoadRegPlusOffsetToAt(rs); |
2111 GenInstrImmediate(LD, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0)); | 2127 GenInstrImmediate(LD, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0)); |
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3396 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { | 3412 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { |
3397 Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize); | 3413 Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize); |
3398 } | 3414 } |
3399 } | 3415 } |
3400 | 3416 |
3401 | 3417 |
3402 } // namespace internal | 3418 } // namespace internal |
3403 } // namespace v8 | 3419 } // namespace v8 |
3404 | 3420 |
3405 #endif // V8_TARGET_ARCH_MIPS64 | 3421 #endif // V8_TARGET_ARCH_MIPS64 |
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