OLD | NEW |
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
(...skipping 1811 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1822 if (is_int16(rs.offset_)) { | 1822 if (is_int16(rs.offset_)) { |
1823 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_); | 1823 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_); |
1824 } else { // Offset > 16 bits, use multiple instructions to load. | 1824 } else { // Offset > 16 bits, use multiple instructions to load. |
1825 LoadRegPlusOffsetToAt(rs); | 1825 LoadRegPlusOffsetToAt(rs); |
1826 GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0)); | 1826 GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0)); |
1827 } | 1827 } |
1828 } | 1828 } |
1829 | 1829 |
1830 | 1830 |
1831 void Assembler::lwl(Register rd, const MemOperand& rs) { | 1831 void Assembler::lwl(Register rd, const MemOperand& rs) { |
| 1832 DCHECK(is_int16(rs.offset_)); |
| 1833 DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) || |
| 1834 IsMipsArchVariant(kMips32r2)); |
1832 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); | 1835 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); |
1833 } | 1836 } |
1834 | 1837 |
1835 | 1838 |
1836 void Assembler::lwr(Register rd, const MemOperand& rs) { | 1839 void Assembler::lwr(Register rd, const MemOperand& rs) { |
| 1840 DCHECK(is_int16(rs.offset_)); |
| 1841 DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) || |
| 1842 IsMipsArchVariant(kMips32r2)); |
1837 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); | 1843 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); |
1838 } | 1844 } |
1839 | 1845 |
1840 | 1846 |
1841 void Assembler::sb(Register rd, const MemOperand& rs) { | 1847 void Assembler::sb(Register rd, const MemOperand& rs) { |
1842 if (is_int16(rs.offset_)) { | 1848 if (is_int16(rs.offset_)) { |
1843 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_); | 1849 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_); |
1844 } else { // Offset > 16 bits, use multiple instructions to store. | 1850 } else { // Offset > 16 bits, use multiple instructions to store. |
1845 LoadRegPlusOffsetToAt(rs); | 1851 LoadRegPlusOffsetToAt(rs); |
1846 GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0)); | 1852 GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0)); |
(...skipping 15 matching lines...) Expand all Loading... |
1862 if (is_int16(rs.offset_)) { | 1868 if (is_int16(rs.offset_)) { |
1863 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_); | 1869 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_); |
1864 } else { // Offset > 16 bits, use multiple instructions to store. | 1870 } else { // Offset > 16 bits, use multiple instructions to store. |
1865 LoadRegPlusOffsetToAt(rs); | 1871 LoadRegPlusOffsetToAt(rs); |
1866 GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0)); | 1872 GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0)); |
1867 } | 1873 } |
1868 } | 1874 } |
1869 | 1875 |
1870 | 1876 |
1871 void Assembler::swl(Register rd, const MemOperand& rs) { | 1877 void Assembler::swl(Register rd, const MemOperand& rs) { |
| 1878 DCHECK(is_int16(rs.offset_)); |
| 1879 DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) || |
| 1880 IsMipsArchVariant(kMips32r2)); |
1872 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); | 1881 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); |
1873 } | 1882 } |
1874 | 1883 |
1875 | 1884 |
1876 void Assembler::swr(Register rd, const MemOperand& rs) { | 1885 void Assembler::swr(Register rd, const MemOperand& rs) { |
| 1886 DCHECK(is_int16(rs.offset_)); |
| 1887 DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) || |
| 1888 IsMipsArchVariant(kMips32r2)); |
1877 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); | 1889 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); |
1878 } | 1890 } |
1879 | 1891 |
1880 | 1892 |
1881 void Assembler::lui(Register rd, int32_t j) { | 1893 void Assembler::lui(Register rd, int32_t j) { |
1882 DCHECK(is_uint16(j)); | 1894 DCHECK(is_uint16(j)); |
1883 GenInstrImmediate(LUI, zero_reg, rd, j); | 1895 GenInstrImmediate(LUI, zero_reg, rd, j); |
1884 } | 1896 } |
1885 | 1897 |
1886 | 1898 |
(...skipping 1269 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3156 | 3168 |
3157 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { | 3169 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { |
3158 Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t)); | 3170 Assembler::FlushICache(isolate, pc, 2 * sizeof(int32_t)); |
3159 } | 3171 } |
3160 } | 3172 } |
3161 | 3173 |
3162 } // namespace internal | 3174 } // namespace internal |
3163 } // namespace v8 | 3175 } // namespace v8 |
3164 | 3176 |
3165 #endif // V8_TARGET_ARCH_MIPS | 3177 #endif // V8_TARGET_ARCH_MIPS |
OLD | NEW |