MIPS: Implement unaligned access instruction.

MIPS: Implement unaligned access instruction.

Implement unaligned access instructions, and tests for corresponding
instruction

BUG=

Committed: https://crrev.com/60497de28ca9d8fc9ce1db56692b2f450b5061a2
Cr-Commit-Position: refs/heads/master@{#35873}

[ivica.bogosavljevic, 2016-04-19 10:28:22]

ivica.bogosavljevic@imgtec.com changed reviewers:
+ akos.palfi@mattakis.com, balazs.kilvady@imgtec.com, ilija.pavlovic@imgtec.com,
marija.antic@imgtec.com, miran.karic@imgtec.com

[ivica.bogosavljevic, 2016-04-19 10:28:22]

PTAL

This is the code that implements unaligned instructions for MIPS. It has been
taken from review https://codereview.chromium.org/1779713009 which is currently
blocked (and we are not yet sure if we are going to complete it, or build
another code review with different approach). Nevertheless, the MIPS related
part is needed for both cases, so here it is as a separate review

[balazs.kilvady, 2016-04-26 12:08:42]

https://codereview.chromium.org/1902743002/diff/1/src/mips/assembler-mips.cc
File src/mips/assembler-mips.cc (right):

https://codereview.chromium.org/1902743002/diff/1/src/mips/assembler-mips.cc#...
src/mips/assembler-mips.cc:1832: DCHECK(is_int16(rs.offset_));
 removed in Release 6 so please add a DCHECK().

https://codereview.chromium.org/1902743002/diff/1/src/mips/assembler-mips.cc#...
src/mips/assembler-mips.cc:1838: DCHECK(is_int16(rs.offset_));
 removed in Release 6 so please add a DCHECK().

https://codereview.chromium.org/1902743002/diff/1/src/mips/assembler-mips.cc#...
src/mips/assembler-mips.cc:1874: DCHECK(is_int16(rs.offset_));
 removed in Release 6 so please add a DCHECK().

https://codereview.chromium.org/1902743002/diff/1/src/mips/assembler-mips.cc#...
src/mips/assembler-mips.cc:1880: DCHECK(is_int16(rs.offset_));
 removed in Release 6 so please add a DCHECK().

[akos.palfi.imgtec, 2016-04-26 13:07:23]

akos.palfi@imgtec.com changed reviewers:
+ akos.palfi@imgtec.com

[akos.palfi.imgtec, 2016-04-26 13:07:24]

Added my first round comments.

https://codereview.chromium.org/1902743002/diff/1/src/mips/macro-assembler-mi...
File src/mips/macro-assembler-mips.cc (right):

https://codereview.chromium.org/1902743002/diff/1/src/mips/macro-assembler-mi...
src/mips/macro-assembler-mips.cc:1198: lw(rd, rs);
From the mips32r6 doc:

"Pre-Release 6: The effective address must be naturally-aligned. If either of
the 2 least-significant bits of the address is
non-zero, an Address Error exception occurs.
Release 6 allows hardware to provide address misalignment support in lieu of
requiring natural alignment."

IIUC, on R6, it's not guaranteed that the HW supports the misaligned access, so
this instruction can throw an exception. However, in this case the kernel
probably do the neccessary fixup, but that would cause a performance drop.
Since the lwl and lwr are removed on R6, it may be problematic to implement
proper unaligned load on R6, so I'm not sure how could we handle this, maybe we
should just leave it as is for now.

https://codereview.chromium.org/1902743002/diff/1/src/mips/macro-assembler-mi...
src/mips/macro-assembler-mips.cc:1202: if (is_int16(rs.offset()) &&
is_int16(rs.offset() + 3)) {
I think, you could use the new constants here:

if (is_int16(rs.offset() + kMipsLwrOffset) && is_int16(rs.offset() +
kMipsLwlOffset)) {

https://codereview.chromium.org/1902743002/diff/1/src/mips/macro-assembler-mi...
src/mips/macro-assembler-mips.cc:1228: if (is_int16(rs.offset()) &&
is_int16(rs.offset() + 3)) {
I think, you could use the new constants here:

if (is_int16(rs.offset() + kMipsSwrOffset) && is_int16(rs.offset() +
kMipsSwlOffset)) {

[akos.palfi.imgtec, 2016-04-27 13:03:35]

lgtm

[ivica.bogosavljevic, 2016-04-28 14:48:32]

The CQ bit was checked by ivica.bogosavljevic@imgtec.com to run a CQ dry run

[commit-bot: I haz the power, 2016-04-28 14:48:44]

Dry run: CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1902743002/20001
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1902743002/20001

[commit-bot: I haz the power, 2016-04-28 15:05:20]

The CQ bit was unchecked by commit-bot@chromium.org

[commit-bot: I haz the power, 2016-04-28 15:05:21]

Dry run: This issue passed the CQ dry run.

[ivica.bogosavljevic, 2016-04-28 15:07:02]

The CQ bit was checked by ivica.bogosavljevic@imgtec.com

[commit-bot: I haz the power, 2016-04-28 15:07:10]

CQ is trying da patch. Follow status at
 https://chromium-cq-status.appspot.com/patch-status/1902743002/20001
View timeline at
 https://chromium-cq-status.appspot.com/patch-timeline/1902743002/20001

[commit-bot: I haz the power, 2016-04-28 15:09:35]

Committed patchset #2 (id:20001)

[commit-bot: I haz the power, 2016-05-01 22:02:46]

Description was changed from

==========
MIPS: Implement unaligned access instruction.

Implement unaligned access instructions, and tests for corresponding
instruction

BUG=
==========

to

==========
MIPS: Implement unaligned access instruction.

Implement unaligned access instructions, and tests for corresponding
instruction

BUG=

Committed: https://crrev.com/60497de28ca9d8fc9ce1db56692b2f450b5061a2
Cr-Commit-Position: refs/heads/master@{#35873}
==========

[commit-bot: I haz the power, 2016-05-01 22:02:47]

Patchset 2 (id:??) landed as
https://crrev.com/60497de28ca9d8fc9ce1db56692b2f450b5061a2
Cr-Commit-Position: refs/heads/master@{#35873}