| Index: src/compiler/mips/instruction-selector-mips.cc
|
| diff --git a/src/compiler/mips/instruction-selector-mips.cc b/src/compiler/mips/instruction-selector-mips.cc
|
| index 2519b9331db35ee20cd7ad2e584d1b560e47685d..9f66a44ea4e0fbbbc9e2aa4e3153bf5bf112278a 100644
|
| --- a/src/compiler/mips/instruction-selector-mips.cc
|
| +++ b/src/compiler/mips/instruction-selector-mips.cc
|
| @@ -1452,6 +1452,29 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
|
| g.UseRegister(left), g.UseRegister(right));
|
| }
|
|
|
| +void InstructionSelector::VisitAtomicLoad(Node* node) {
|
| + LoadRepresentation load_rep = LoadRepresentationOf(node->op());
|
| + OperandGenerator g(this);
|
| + Node* base = node->InputAt(0);
|
| + Node* index = node->InputAt(1);
|
| + ArchOpcode opcode = kArchNop;
|
| + switch (load_rep.representation()) {
|
| + case MachineRepresentation::kWord8:
|
| + opcode = load_rep.IsSigned() ? kAtomicLoadInt8 : kAtomicLoadUint8;
|
| + break;
|
| + case MachineRepresentation::kWord16:
|
| + opcode = load_rep.IsSigned() ? kAtomicLoadInt16 : kAtomicLoadUint16;
|
| + break;
|
| + case MachineRepresentation::kWord32:
|
| + opcode = kAtomicLoadWord32;
|
| + break;
|
| + default:
|
| + UNREACHABLE();
|
| + return;
|
| + }
|
| + Emit(opcode | AddressingModeField::encode(kMode_MRI),
|
| + g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(index));
|
| +}
|
|
|
| // static
|
| MachineOperatorBuilder::Flags
|
|
|