Subzero: Allow per-method controls.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 1381 matching lines @@
   // bit-manipulation problems below.
   const uint32_t AlignmentParam = std::max(1u, Instr->getAlignInBytes());
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
   assert(llvm::isPowerOf2_32(Traits::X86_STACK_ALIGNMENT_BYTES));
 
   const uint32_t Alignment =
       std::max(AlignmentParam, Traits::X86_STACK_ALIGNMENT_BYTES);
   const bool OverAligned = Alignment > Traits::X86_STACK_ALIGNMENT_BYTES;
-  const bool OptM1 = getFlags().getOptLevel() == Opt_m1;
+  const bool OptM1 = Func->getOptLevel() == Opt_m1;
   const bool AllocaWithKnownOffset = Instr->getKnownFrameOffset();
   const bool UseFramePointer =
       hasFramePointer() || OverAligned || !AllocaWithKnownOffset || OptM1;
 
   if (UseFramePointer)
     setHasFramePointer();
 
   Variable *esp = getPhysicalRegister(getStackReg(), Traits::WordType);
   if (OverAligned) {
     _and(esp, Ctx->getConstantInt32(-Alignment));
@@ skipping 109 matching lines @@
 /// Strength-reduce scalar integer multiplication by a constant (for i32 or
 /// narrower) for certain constants. The lea instruction can be used to multiply
 /// by 3, 5, or 9, and the lsh instruction can be used to multiply by powers of
 /// 2. These can be combined such that e.g. multiplying by 100 can be done as 2
 /// lea-based multiplies by 5, combined with left-shifting by 2.
 template <typename TraitsType>
 bool TargetX86Base<TraitsType>::optimizeScalarMul(Variable *Dest, Operand *Src0,
                                                   int32_t Src1) {
   // Disable this optimization for Om1 and O0, just to keep things simple
   // there.
-  if (getFlags().getOptLevel() < Opt_1)
+  if (Func->getOptLevel() < Opt_1)
     return false;
   Type Ty = Dest->getType();
   if (Src1 == -1) {
     Variable *T = nullptr;
     _mov(T, Src0);
     _neg(T);
     _mov(Dest, T);
     return true;
   }
   if (Src1 == 0) {
@@ skipping 673 matching lines @@
     }
     T_edx = makeReg(Ty, Edx);
     _mov(T, Src0, Eax);
     _mov(T_edx, Ctx->getConstantZero(Ty));
     _div(T, Src1, T_edx);
     _mov(Dest, T);
   } break;
   case InstArithmetic::Sdiv:
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
-    if (false && getFlags().getOptLevel() >= Opt_1) {
+    if (false && Func->getOptLevel() >= Opt_1) {
       // Optimize division by constant power of 2, but not for Om1 or O0, just
       // to keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
         const int32_t Divisor = C->getValue();
         const uint32_t UDivisor = Divisor;
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           // LLVM does the following for dest=src/(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
@@ skipping 69 matching lines @@
     }
     T_edx = makeReg(Ty, Edx);
     _mov(T_edx, Ctx->getConstantZero(Ty));
     _mov(T, Src0, Eax);
     _div(T_edx, Src1, T);
     _mov(Dest, T_edx);
   } break;
   case InstArithmetic::Srem: {
     // TODO(stichnot): Enable this after doing better performance and cross
     // testing.
-    if (false && getFlags().getOptLevel() >= Opt_1) {
+    if (false && Func->getOptLevel() >= Opt_1) {
       // Optimize mod by constant power of 2, but not for Om1 or O0, just to
       // keep things simple there.
       if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) {
         const int32_t Divisor = C->getValue();
         const uint32_t UDivisor = Divisor;
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           // LLVM does the following for dest=src%(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
@@ skipping 1972 matching lines @@
   constexpr bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
 }
 
 template <typename TraitsType>
 bool TargetX86Base<TraitsType>::tryOptimizedCmpxchgCmpBr(Variable *Dest,
                                                          Operand *PtrToMem,
                                                          Operand *Expected,
                                                          Operand *Desired) {
-  if (getFlags().getOptLevel() == Opt_m1)
+  if (Func->getOptLevel() == Opt_m1)
     return false;
   // Peek ahead a few instructions and see how Dest is used.
   // It's very common to have:
   //
   // %x = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* ptr, i32 %expected, ...)
   // [%y_phi = ...] // list of phi stores
   // %p = icmp eq i32 %x, %expected
   // br i1 %p, label %l1, label %l2
   //
   // which we can optimize into:
@@ skipping 2689 matching lines @@
   uint32_t TyIndex = llvm::findLastSet(Size, llvm::ZB_Undefined);
   if (!llvm::isPowerOf2_32(Size))
     ++TyIndex;
   uint32_t MaxIndex = MaxSize == NoSizeLimit
                           ? llvm::array_lengthof(TypeForSize) - 1
                           : llvm::findLastSet(MaxSize, llvm::ZB_Undefined);
   return TypeForSize[std::min(TyIndex, MaxIndex)];
 }
 
 template <typename TraitsType> void TargetX86Base<TraitsType>::postLower() {
-  if (getFlags().getOptLevel() == Opt_m1)
+  if (Func->getOptLevel() == Opt_m1)
     return;
   markRedefinitions();
   Context.availabilityUpdate();
 }
 
 template <typename TraitsType>
 void TargetX86Base<TraitsType>::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<RegNumT> &Permutation,
     const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   Traits::makeRandomRegisterPermutation(Func, Permutation, ExcludeRegisters,
@@ skipping 380 matching lines @@
 void TargetDataX86<TraitsType>::lowerGlobals(
     const VariableDeclarationList &Vars, const std::string &SectionSuffix) {
   const bool IsPIC = getFlags().getUseNonsfi();
   switch (getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
     Writer->writeDataSection(Vars, Traits::FK_Abs, SectionSuffix, IsPIC);
   } break;
   case FT_Asm:
   case FT_Iasm: {
-    const std::string TranslateOnly = getFlags().getTranslateOnly();
     OstreamLocker L(Ctx);
     for (const VariableDeclaration *Var : Vars) {
-      if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
+      if (getFlags().matchTranslateOnly(Var->getName(), 0)) {
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 } // end of namespace X86NAMESPACE
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H