Subzero: Allow per-method controls.

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 6799 matching lines @@
                                    const std::string &SectionSuffix) {
   const bool IsPIC = getFlags().getUseNonsfi();
   switch (getFlags().getOutFileType()) {
   case FT_Elf: {
     ELFObjectWriter *Writer = Ctx->getObjectWriter();
     Writer->writeDataSection(Vars, llvm::ELF::R_ARM_ABS32, SectionSuffix,
                              IsPIC);
   } break;
   case FT_Asm:
   case FT_Iasm: {
-    const std::string TranslateOnly = getFlags().getTranslateOnly();
     OstreamLocker _(Ctx);
     for (const VariableDeclaration *Var : Vars) {
-      if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
+      if (getFlags().matchTranslateOnly(Var->getName(), 0)) {
         emitGlobal(*Var, SectionSuffix);
       }
     }
   } break;
   }
 }
 
 namespace {
 template <typename T> struct ConstantPoolEmitterTraits;
 
@@ skipping 164 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice