MIPS: [Atomics] Remove Atomics code stubs; use TF ops.

src/mips64/assembler-mips64.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 2237 matching lines @@
 }
 
 
 void Assembler::tne(Register rs, Register rt, uint16_t code) {
   DCHECK(is_uint10(code));
   Instr instr =
       SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
   emit(instr);
 }
 
+void Assembler::sync() {
+  Instr sync_instr = SPECIAL | SYNC;
+  emit(sync_instr);
+}
 
 // Move from HI/LO register.
 
 void Assembler::mfhi(Register rd) {
   GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
 }
 
 
 void Assembler::mflo(Register rd) {
   GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
@@ skipping 1124 matching lines @@
   if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
     Assembler::FlushICache(isolate, pc, 4 * Assembler::kInstrSize);
   }
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS64