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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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1184 break; | 1184 break; |
1185 case TLTU: | 1185 case TLTU: |
1186 Format(instr, "tltu 'rs, 'rt, code: 'code"); | 1186 Format(instr, "tltu 'rs, 'rt, code: 'code"); |
1187 break; | 1187 break; |
1188 case TEQ: | 1188 case TEQ: |
1189 Format(instr, "teq 'rs, 'rt, code: 'code"); | 1189 Format(instr, "teq 'rs, 'rt, code: 'code"); |
1190 break; | 1190 break; |
1191 case TNE: | 1191 case TNE: |
1192 Format(instr, "tne 'rs, 'rt, code: 'code"); | 1192 Format(instr, "tne 'rs, 'rt, code: 'code"); |
1193 break; | 1193 break; |
| 1194 case SYNC: |
| 1195 Format(instr, "sync"); |
| 1196 break; |
1194 case MOVZ: | 1197 case MOVZ: |
1195 Format(instr, "movz 'rd, 'rs, 'rt"); | 1198 Format(instr, "movz 'rd, 'rs, 'rt"); |
1196 break; | 1199 break; |
1197 case MOVN: | 1200 case MOVN: |
1198 Format(instr, "movn 'rd, 'rs, 'rt"); | 1201 Format(instr, "movn 'rd, 'rs, 'rt"); |
1199 break; | 1202 break; |
1200 case MOVCI: | 1203 case MOVCI: |
1201 if (instr->Bit(16)) { | 1204 if (instr->Bit(16)) { |
1202 Format(instr, "movt 'rd, 'rs, 'bc"); | 1205 Format(instr, "movt 'rd, 'rs, 'bc"); |
1203 } else { | 1206 } else { |
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1763 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 1766 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
1764 } | 1767 } |
1765 } | 1768 } |
1766 | 1769 |
1767 | 1770 |
1768 #undef UNSUPPORTED | 1771 #undef UNSUPPORTED |
1769 | 1772 |
1770 } // namespace disasm | 1773 } // namespace disasm |
1771 | 1774 |
1772 #endif // V8_TARGET_ARCH_MIPS | 1775 #endif // V8_TARGET_ARCH_MIPS |
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