OLD | NEW |
1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
(...skipping 4014 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4025 } | 4025 } |
4026 | 4026 |
4027 | 4027 |
4028 void CodePatcher::EmitCondition(Condition cond) { | 4028 void CodePatcher::EmitCondition(Condition cond) { |
4029 Instr instr = Assembler::instr_at(masm_.pc_); | 4029 Instr instr = Assembler::instr_at(masm_.pc_); |
4030 instr = (instr & ~kCondMask) | cond; | 4030 instr = (instr & ~kCondMask) | cond; |
4031 masm_.emit(instr); | 4031 masm_.emit(instr); |
4032 } | 4032 } |
4033 | 4033 |
4034 | 4034 |
4035 void MacroAssembler::FlooringDiv(Register result, | |
4036 Register dividend, | |
4037 int32_t divisor) { | |
4038 ASSERT(!dividend.is(result)); | |
4039 ASSERT(!dividend.is(ip)); | |
4040 ASSERT(!result.is(ip)); | |
4041 MultiplierAndShift ms(divisor); | |
4042 mov(ip, Operand(ms.multiplier())); | |
4043 smull(result, ip, dividend, ip); | |
4044 if (divisor > 0 && ms.multiplier() < 0) add(ip, ip, Operand(dividend)); | |
4045 if (divisor < 0 && ms.multiplier() > 0) sub(ip, ip, Operand(dividend)); | |
4046 if (ms.shift() > 0) mov(ip, Operand(ip, ASR, ms.shift())); | |
4047 add(result, ip, Operand(dividend, LSR, 31)); | |
4048 } | |
4049 | |
4050 | |
4051 } } // namespace v8::internal | 4035 } } // namespace v8::internal |
4052 | 4036 |
4053 #endif // V8_TARGET_ARCH_ARM | 4037 #endif // V8_TARGET_ARCH_ARM |
OLD | NEW |