[Subzero][MIPS] Implement conditional branches and integer comparisons

src/IceTargetLoweringMIPS32.cpp

 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 938 matching lines @@
 }
 
 void TargetMIPS32::lowerExtractElement(const InstExtractElement *Instr) {
   UnimplementedLoweringError(this, Instr);
 }
 
 void TargetMIPS32::lowerFcmp(const InstFcmp *Instr) {
   UnimplementedLoweringError(this, Instr);
 }
 
+void TargetMIPS32::lower64Icmp(const InstIcmp *Instr) {
+  UnimplementedLoweringError(this, Instr);
+  return;
+}
+
 void TargetMIPS32::lowerIcmp(const InstIcmp *Instr) {
-  UnimplementedLoweringError(this, Instr);
+  auto *Src0 = Instr->getSrc(0);
+  auto *Src1 = Instr->getSrc(1);
+  if (Src0->getType() == IceType_i64) {
+    lower64Icmp(Instr);
+    return;
+  }
+  Variable *Dest = Instr->getDest();
+  if (isVectorType(Dest->getType())) {
+    UnimplementedLoweringError(this, Instr);
+    return;
+  }
+  InstIcmp::ICond Cond = Instr->getCondition();
+  auto *Src0R = legalizeToReg(Src0);
+  auto *Src1R = legalizeToReg(Src1);
+  switch (Cond) {
+  case InstIcmp::Eq: {
+    auto *DestT = I32Reg();
+    auto *T = I32Reg();
+    _xor(T, Src0R, Src1R);
+    _sltiu(DestT, T, 1);
+    _mov(Dest, DestT);
+    return;
+  }
+  case InstIcmp::Ne: {
+    auto *DestT = I32Reg();
+    auto *T = I32Reg();
+    auto *Zero = getZero();
+    _xor(T, Src0R, Src1R);
+    _sltu(DestT, Zero, T);
+    _mov(Dest, DestT);
+    return;
+  }
+  case InstIcmp::Ugt: {
+    auto *DestT = I32Reg();
+    _sltu(DestT, Src1R, Src0R);
+    _mov(Dest, DestT);
+    return;
+  }
+  case InstIcmp::Uge: {
+    auto *DestT = I32Reg();
+    auto *T = I32Reg();
+    _sltu(T, Src0R, Src1R);
+    _xori(DestT, T, 1);
+    _mov(Dest, DestT);
+    return;
+  }
+  case InstIcmp::Ult: {
+    auto *DestT = I32Reg();
+    _sltu(DestT, Src0R, Src1R);
+    _mov(Dest, DestT);
+    return;
+  }
+  case InstIcmp::Ule: {
+    auto *DestT = I32Reg();
+    auto *T = I32Reg();
+    _sltu(T, Src1R, Src0R);
+    _xori(DestT, T, 1);
+    _mov(Dest, DestT);
+    return;
+  }
+  case InstIcmp::Sgt: {
+    auto *DestT = I32Reg();
+    _slt(DestT, Src1R, Src0R);
+    _mov(Dest, DestT);
+    return;
+  }
+  case InstIcmp::Sge: {
+    auto *DestT = I32Reg();
+    auto *T = I32Reg();
+    _slt(T, Src1R, Src0R);
+    _xori(DestT, T, 1);
+    _mov(Dest, DestT);
+    return;
+  }
+  case InstIcmp::Slt: {
+    auto *DestT = I32Reg();
+    _slt(DestT, Src0R, Src1R);
+    _mov(Dest, DestT);
+    return;
+  }
+  case InstIcmp::Sle: {
+    auto *DestT = I32Reg();
+    auto *T = I32Reg();
+    _slt(T, Src1R, Src0R);
+    _xori(DestT, T, 1);
+    _mov(Dest, DestT);
+    return;
+  }
+  default:
+    llvm_unreachable("Invalid ICmp operator");
+    return;
+  }
 }
 
 void TargetMIPS32::lowerInsertElement(const InstInsertElement *Instr) {
   UnimplementedLoweringError(this, Instr);
 }
 
 void TargetMIPS32::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
   switch (Instr->getIntrinsicInfo().ID) {
   case Intrinsics::AtomicCmpxchg: {
     UnimplementedLoweringError(this, Instr);
@@ skipping 351 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice