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1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// | 1 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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1013 return; | 1013 return; |
1014 Func->deletePhis(); | 1014 Func->deletePhis(); |
1015 if (Func->hasError()) | 1015 if (Func->hasError()) |
1016 return; | 1016 return; |
1017 Func->dump("After Phi lowering"); | 1017 Func->dump("After Phi lowering"); |
1018 } | 1018 } |
1019 | 1019 |
1020 // Address mode optimization. | 1020 // Address mode optimization. |
1021 Func->getVMetadata()->init(VMK_SingleDefs); | 1021 Func->getVMetadata()->init(VMK_SingleDefs); |
1022 Func->doAddressOpt(); | 1022 Func->doAddressOpt(); |
| 1023 Func->materializeVectorShuffles(); |
1023 | 1024 |
1024 // Argument lowering | 1025 // Argument lowering |
1025 Func->doArgLowering(); | 1026 Func->doArgLowering(); |
1026 | 1027 |
1027 // Target lowering. This requires liveness analysis for some parts of the | 1028 // Target lowering. This requires liveness analysis for some parts of the |
1028 // lowering decisions, such as compare/branch fusing. If non-lightweight | 1029 // lowering decisions, such as compare/branch fusing. If non-lightweight |
1029 // liveness analysis is used, the instructions need to be renumbered first. | 1030 // liveness analysis is used, the instructions need to be renumbered first. |
1030 // TODO: This renumbering should only be necessary if we're actually | 1031 // TODO: This renumbering should only be necessary if we're actually |
1031 // calculating live intervals, which we only do for register allocation. | 1032 // calculating live intervals, which we only do for register allocation. |
1032 Func->renumberInstructions(); | 1033 Func->renumberInstructions(); |
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5805 _ret(getPhysicalRegister(RegARM32::Reg_lr), Reg); | 5806 _ret(getPhysicalRegister(RegARM32::Reg_lr), Reg); |
5806 | 5807 |
5807 // Add a fake use of sp to make sure sp stays alive for the entire function. | 5808 // Add a fake use of sp to make sure sp stays alive for the entire function. |
5808 // Otherwise post-call sp adjustments get dead-code eliminated. | 5809 // Otherwise post-call sp adjustments get dead-code eliminated. |
5809 // TODO: Are there more places where the fake use should be inserted? E.g. | 5810 // TODO: Are there more places where the fake use should be inserted? E.g. |
5810 // "void f(int n){while(1) g(n);}" may not have a ret instruction. | 5811 // "void f(int n){while(1) g(n);}" may not have a ret instruction. |
5811 Variable *SP = getPhysicalRegister(RegARM32::Reg_sp); | 5812 Variable *SP = getPhysicalRegister(RegARM32::Reg_sp); |
5812 Context.insert<InstFakeUse>(SP); | 5813 Context.insert<InstFakeUse>(SP); |
5813 } | 5814 } |
5814 | 5815 |
| 5816 void TargetARM32::lowerShuffleVector(const InstShuffleVector *Instr) { |
| 5817 auto *Dest = Instr->getDest(); |
| 5818 const Type DestTy = Dest->getType(); |
| 5819 |
| 5820 auto *T = makeReg(DestTy); |
| 5821 |
| 5822 switch (DestTy) { |
| 5823 default: |
| 5824 break; |
| 5825 // TODO(jpp): figure out how to properly lower this without scalarization. |
| 5826 } |
| 5827 |
| 5828 // Unoptimized shuffle. Perform a series of inserts and extracts. |
| 5829 Context.insert<InstFakeDef>(T); |
| 5830 auto *Src0 = llvm::cast<Variable>(Instr->getSrc(0)); |
| 5831 auto *Src1 = llvm::cast<Variable>(Instr->getSrc(1)); |
| 5832 const SizeT NumElements = typeNumElements(DestTy); |
| 5833 const Type ElementType = typeElementType(DestTy); |
| 5834 for (SizeT I = 0; I < Instr->getNumIndexes(); ++I) { |
| 5835 auto *Index = Instr->getIndex(I); |
| 5836 const SizeT Elem = Index->getValue(); |
| 5837 auto *ExtElmt = makeReg(ElementType); |
| 5838 if (Elem < NumElements) { |
| 5839 lowerExtractElement( |
| 5840 InstExtractElement::create(Func, ExtElmt, Src0, Index)); |
| 5841 } else { |
| 5842 lowerExtractElement(InstExtractElement::create( |
| 5843 Func, ExtElmt, Src1, |
| 5844 Ctx->getConstantInt32(Index->getValue() - NumElements))); |
| 5845 } |
| 5846 auto *NewT = makeReg(DestTy); |
| 5847 lowerInsertElement(InstInsertElement::create(Func, NewT, T, ExtElmt, |
| 5848 Ctx->getConstantInt32(I))); |
| 5849 T = NewT; |
| 5850 } |
| 5851 _mov(Dest, T); |
| 5852 } |
| 5853 |
5815 void TargetARM32::lowerSelect(const InstSelect *Instr) { | 5854 void TargetARM32::lowerSelect(const InstSelect *Instr) { |
5816 Variable *Dest = Instr->getDest(); | 5855 Variable *Dest = Instr->getDest(); |
5817 Type DestTy = Dest->getType(); | 5856 Type DestTy = Dest->getType(); |
5818 Operand *SrcT = Instr->getTrueOperand(); | 5857 Operand *SrcT = Instr->getTrueOperand(); |
5819 Operand *SrcF = Instr->getFalseOperand(); | 5858 Operand *SrcF = Instr->getFalseOperand(); |
5820 Operand *Condition = Instr->getCondition(); | 5859 Operand *Condition = Instr->getCondition(); |
5821 | 5860 |
5822 if (!isVectorType(DestTy)) { | 5861 if (!isVectorType(DestTy)) { |
5823 lowerInt1ForSelect(Dest, Condition, legalizeUndef(SrcT), | 5862 lowerInt1ForSelect(Dest, Condition, legalizeUndef(SrcT), |
5824 legalizeUndef(SrcF)); | 5863 legalizeUndef(SrcF)); |
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7107 // However, for compatibility with current NaCl LLVM, don't claim that. | 7146 // However, for compatibility with current NaCl LLVM, don't claim that. |
7108 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; | 7147 Str << ".eabi_attribute 14, 3 @ Tag_ABI_PCS_R9_use: Not used\n"; |
7109 } | 7148 } |
7110 | 7149 |
7111 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; | 7150 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM]; |
7112 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; | 7151 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM]; |
7113 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; | 7152 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM]; |
7114 | 7153 |
7115 } // end of namespace ARM32 | 7154 } // end of namespace ARM32 |
7116 } // end of namespace Ice | 7155 } // end of namespace Ice |
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