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Issue 1896733002: S390: Fix popcnt64 should use lgbr for final dst. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <assert.h> // For assert 5 #include <assert.h> // For assert
6 #include <limits.h> // For LONG_MIN, LONG_MAX. 6 #include <limits.h> // For LONG_MIN, LONG_MAX.
7 7
8 #if V8_TARGET_ARCH_S390 8 #if V8_TARGET_ARCH_S390
9 9
10 #include "src/base/bits.h" 10 #include "src/base/bits.h"
(...skipping 5306 matching lines...) Expand 10 before | Expand all | Expand 10 after
5317 5317
5318 void MacroAssembler::Popcnt32(Register dst, Register src) { 5318 void MacroAssembler::Popcnt32(Register dst, Register src) {
5319 DCHECK(!src.is(r0)); 5319 DCHECK(!src.is(r0));
5320 DCHECK(!dst.is(r0)); 5320 DCHECK(!dst.is(r0));
5321 5321
5322 popcnt(dst, src); 5322 popcnt(dst, src);
5323 ShiftRight(r0, dst, Operand(16)); 5323 ShiftRight(r0, dst, Operand(16));
5324 ar(dst, r0); 5324 ar(dst, r0);
5325 ShiftRight(r0, dst, Operand(8)); 5325 ShiftRight(r0, dst, Operand(8));
5326 ar(dst, r0); 5326 ar(dst, r0);
5327 lbr(dst, dst); 5327 LoadB(dst, dst);
5328 } 5328 }
5329 5329
5330 #ifdef V8_TARGET_ARCH_S390X 5330 #ifdef V8_TARGET_ARCH_S390X
5331 void MacroAssembler::Popcnt64(Register dst, Register src) { 5331 void MacroAssembler::Popcnt64(Register dst, Register src) {
5332 DCHECK(!src.is(r0)); 5332 DCHECK(!src.is(r0));
5333 DCHECK(!dst.is(r0)); 5333 DCHECK(!dst.is(r0));
5334 5334
5335 popcnt(dst, src); 5335 popcnt(dst, src);
5336 ShiftRightP(r0, dst, Operand(32)); 5336 ShiftRightP(r0, dst, Operand(32));
5337 AddP(dst, r0); 5337 AddP(dst, r0);
5338 ShiftRightP(r0, dst, Operand(16)); 5338 ShiftRightP(r0, dst, Operand(16));
5339 AddP(dst, r0); 5339 AddP(dst, r0);
5340 ShiftRightP(r0, dst, Operand(8)); 5340 ShiftRightP(r0, dst, Operand(8));
5341 AddP(dst, r0); 5341 AddP(dst, r0);
5342 lbr(dst, dst); 5342 LoadB(dst, dst);
5343 } 5343 }
5344 #endif 5344 #endif
5345 5345
5346 #ifdef DEBUG 5346 #ifdef DEBUG
5347 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, 5347 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4,
5348 Register reg5, Register reg6, Register reg7, Register reg8, 5348 Register reg5, Register reg6, Register reg7, Register reg8,
5349 Register reg9, Register reg10) { 5349 Register reg9, Register reg10) {
5350 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() + 5350 int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() + reg3.is_valid() +
5351 reg4.is_valid() + reg5.is_valid() + reg6.is_valid() + 5351 reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
5352 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() + 5352 reg7.is_valid() + reg8.is_valid() + reg9.is_valid() +
(...skipping 71 matching lines...) Expand 10 before | Expand all | Expand 10 after
5424 } 5424 }
5425 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift)); 5425 if (mag.shift > 0) ShiftRightArith(result, result, Operand(mag.shift));
5426 ExtractBit(r0, dividend, 31); 5426 ExtractBit(r0, dividend, 31);
5427 AddP(result, r0); 5427 AddP(result, r0);
5428 } 5428 }
5429 5429
5430 } // namespace internal 5430 } // namespace internal
5431 } // namespace v8 5431 } // namespace v8
5432 5432
5433 #endif // V8_TARGET_ARCH_S390 5433 #endif // V8_TARGET_ARCH_S390
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