Subzero. ARM32. De-scalarizes icmp and fcmp for vectors.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 839 matching lines @@
   }
   void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstARM32Vadd>(Dest, Src0, Src1);
   }
   void _vand(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstARM32Vand>(Dest, Src0, Src1);
   }
   InstARM32Vbsl *_vbsl(Variable *Dest, Variable *Src0, Variable *Src1) {
     return Context.insert<InstARM32Vbsl>(Dest, Src0, Src1);
   }
+  void _vceq(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstARM32Vceq>(Dest, Src0, Src1);
+  }
+  InstARM32Vcge *_vcge(Variable *Dest, Variable *Src0, Variable *Src1) {
+    return Context.insert<InstARM32Vcge>(Dest, Src0, Src1);
+  }
+  InstARM32Vcgt *_vcgt(Variable *Dest, Variable *Src0, Variable *Src1) {
+    return Context.insert<InstARM32Vcgt>(Dest, Src0, Src1);
+  }
   void _vcvt(Variable *Dest, Variable *Src, InstARM32Vcvt::VcvtVariant Variant,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Vcvt>(Dest, Src, Variant, Pred);
   }
   void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstARM32Vdiv>(Dest, Src0, Src1);
   }
   void _vcmp(Variable *Src0, Variable *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert<InstARM32Vcmp>(Src0, Src1, Pred);
@@ skipping 10 matching lines @@
   }
   void _vmla(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstARM32Vmla>(Dest, Src0, Src1);
   }
   void _vmls(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstARM32Vmls>(Dest, Src0, Src1);
   }
   void _vmul(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstARM32Vmul>(Dest, Src0, Src1);
   }
+  void _vmvn(Variable *Dest, Variable *Src0) {
+    Context.insert<InstARM32Vmvn>(Dest, Src0, CondARM32::AL);
+  }
   void _vneg(Variable *Dest, Variable *Src0) {
     Context.insert<InstARM32Vneg>(Dest, Src0, CondARM32::AL)
         ->setSignType(InstARM32::FS_Signed);
   }
   void _vorr(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstARM32Vorr>(Dest, Src0, Src1);
   }
   InstARM32Vshl *_vshl(Variable *Dest, Variable *Src0, Variable *Src1) {
     return Context.insert<InstARM32Vshl>(Dest, Src0, Src1);
   }
@@ skipping 453 matching lines @@
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H