Subzero. ARM32. De-scalarizes icmp and fcmp for vectors.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 410 matching lines @@
     Sxt,
     Trap,
     Tst,
     Udiv,
     Umull,
     Uxt,
     Vabs,
     Vadd,
     Vand,
     Vbsl,
+    Vceq,
+    Vcge,
+    Vcgt,
     Vcmp,
     Vcvt,
     Vdiv,
     Veor,
     Vmla,
     Vmls,
     Vmrs,
     Vmul,
+    Vmvn,
     Vneg,
     Vorr,
     Vshl,
     Vshr,
     Vsqrt,
     Vsub
   };
 
   static constexpr size_t InstSize = sizeof(uint32_t);
 
   static CondARM32::Cond getOppositeCondition(CondARM32::Cond Cond);
 
   /// Called inside derived methods emit() to communicate that multiple
   /// instructions are being generated. Used by emitIAS() methods to
   /// generate textual fixups for instructions that are not yet
   /// implemented.
   void startNextInst(const Cfg *Func) const;
 
   /// FPSign is used for certain vector instructions (particularly, right
   /// shifts) that require an operand sign specification.
   enum FPSign {
     FS_None,
     FS_Signed,
     FS_Unsigned,
   };
   /// Shared emit routines for common forms of instructions.
   /// @{
   static void emitThreeAddrFP(const char *Opcode, FPSign Sign,
-                              const InstARM32 *Instr, const Cfg *Func);
+                              const InstARM32 *Instr, const Cfg *Func,
+                              Type OpType);
   static void emitFourAddrFP(const char *Opcode, FPSign Sign,
                              const InstARM32 *Instr, const Cfg *Func);
   /// @}
 
   void dump(const Cfg *Func) const override;
 
   void emitIAS(const Cfg *Func) const override;
 
 protected:
   InstARM32(Cfg *Func, InstKindARM32 Kind, SizeT Maxsrcs, Variable *Dest)
@@ skipping 297 matching lines @@
   /// Create a vector/FP binary-op instruction like vadd, and vsub. Everything
   /// must be a register.
   static InstARM32ThreeAddrFP *create(Cfg *Func, Variable *Dest, Variable *Src0,
                                       Variable *Src1) {
     return new (Func->allocate<InstARM32ThreeAddrFP>())
         InstARM32ThreeAddrFP(Func, Dest, Src0, Src1);
   }
   void emit(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
-    emitThreeAddrFP(Opcode, Sign, this, Func);
+    const Type OpType = (isVectorCompare() ? getSrc(0) : getDest())->getType();
+    emitThreeAddrFP(Opcode, Sign, this, Func, OpType);
   }
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
     dumpDest(Func);
-    Str << " = ";
-    Str << Opcode << "." << getDest()->getType() << " ";
+    const Type OpType = (isVectorCompare() ? getSrc(0) : getDest())->getType();
+    Str << " = " << Opcode << "." << OpType << " ";
     dumpSources(Func);
   }
   static bool classof(const Inst *Instr) { return isClassof(Instr, K); }
 
 protected:
   FPSign Sign = FS_None;
 
   InstARM32ThreeAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1)
       : InstARM32(Func, K, 2, Dest) {
     addSource(Src0);
     addSource(Src1);
   }
 
   static const char *Opcode;
+
+private:
+  static constexpr bool isVectorCompare() {
+    return K == InstARM32::Vceq || K == InstARM32::Vcgt || K == InstARM32::Vcge;
+  }
 };
 
 template <InstARM32::InstKindARM32 K>
 class InstARM32ThreeAddrSignAwareFP : public InstARM32ThreeAddrFP<K> {
   InstARM32ThreeAddrSignAwareFP() = delete;
   InstARM32ThreeAddrSignAwareFP(const InstARM32ThreeAddrSignAwareFP &) = delete;
   InstARM32ThreeAddrSignAwareFP &
   operator=(const InstARM32ThreeAddrSignAwareFP &) = delete;
 
 public:
@@ skipping 168 matching lines @@
 using InstARM32Orr = InstARM32ThreeAddrGPR<InstARM32::Orr>;
 using InstARM32Rsb = InstARM32ThreeAddrGPR<InstARM32::Rsb>;
 using InstARM32Rsc = InstARM32ThreeAddrGPR<InstARM32::Rsc>;
 using InstARM32Sbc = InstARM32ThreeAddrGPR<InstARM32::Sbc>;
 using InstARM32Sdiv = InstARM32ThreeAddrGPR<InstARM32::Sdiv>;
 using InstARM32Sub = InstARM32ThreeAddrGPR<InstARM32::Sub>;
 using InstARM32Udiv = InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 using InstARM32Vadd = InstARM32ThreeAddrFP<InstARM32::Vadd>;
 using InstARM32Vand = InstARM32ThreeAddrFP<InstARM32::Vand>;
 using InstARM32Vbsl = InstARM32ThreeAddrFP<InstARM32::Vbsl>;
+using InstARM32Vceq = InstARM32ThreeAddrFP<InstARM32::Vceq>;
+using InstARM32Vcge = InstARM32ThreeAddrSignAwareFP<InstARM32::Vcge>;
+using InstARM32Vcgt = InstARM32ThreeAddrSignAwareFP<InstARM32::Vcgt>;
 using InstARM32Vdiv = InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 using InstARM32Veor = InstARM32ThreeAddrFP<InstARM32::Veor>;
 using InstARM32Vmla = InstARM32FourAddrFP<InstARM32::Vmla>;
 using InstARM32Vmls = InstARM32FourAddrFP<InstARM32::Vmls>;
 using InstARM32Vmul = InstARM32ThreeAddrFP<InstARM32::Vmul>;
+using InstARM32Vmvn = InstARM32UnaryopFP<InstARM32::Vmvn>;
 using InstARM32Vneg = InstARM32UnaryopSignAwareFP<InstARM32::Vneg>;
 using InstARM32Vorr = InstARM32ThreeAddrFP<InstARM32::Vorr>;
 using InstARM32Vshl = InstARM32ThreeAddrSignAwareFP<InstARM32::Vshl>;
 using InstARM32Vshr = InstARM32ThreeAddrSignAwareFP<InstARM32::Vshr>;
 using InstARM32Vsub = InstARM32ThreeAddrFP<InstARM32::Vsub>;
 using InstARM32Ldr = InstARM32LoadBase<InstARM32::Ldr>;
 using InstARM32Ldrex = InstARM32LoadBase<InstARM32::Ldrex>;
 /// MovT leaves the bottom bits alone so dest is also a source. This helps
 /// indicate that a previous MovW setting dest is not dead code.
 using InstARM32Movt = InstARM32TwoAddrGPR<InstARM32::Movt>;
@@ skipping 597 matching lines @@
 // violations and link errors.
 
 template <> void InstARM32Ldr::emit(const Cfg *Func) const;
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace ARM32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H