Subzero. ARM32. De-scalarizes icmp and fcmp for vectors.

src/IceInstARM32.cpp

 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 210 matching lines @@
   Str << "\t" << Opcode << (SetFlags ? "s" : "") << Instr->getPredicate()
       << "\t";
   Instr->getDest()->emit(Func);
   Str << ", ";
   Instr->getSrc(0)->emit(Func);
   Str << ", ";
   Instr->getSrc(1)->emit(Func);
 }
 
 void InstARM32::emitThreeAddrFP(const char *Opcode, FPSign SignType,
-                                const InstARM32 *Instr, const Cfg *Func) {
+                                const InstARM32 *Instr, const Cfg *Func,
+                                Type OpType) {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Instr->getSrcSize() == 2);
-  Str << "\t" << Opcode
-      << getVWidthString(Instr->getDest()->getType(), SignType) << "\t";
+  Str << "\t" << Opcode << getVWidthString(OpType, SignType) << "\t";
   Instr->getDest()->emit(Func);
   Str << ", ";
   Instr->getSrc(0)->emit(Func);
   Str << ", ";
   Instr->getSrc(1)->emit(Func);
 }
 
 void InstARM32::emitFourAddrFP(const char *Opcode, FPSign SignType,
                                const InstARM32 *Instr, const Cfg *Func) {
   if (!BuildDefs::dump())
@@ skipping 449 matching lines @@
   case IceType_v8i1:
   case IceType_v16i1:
   case IceType_v16i8:
   case IceType_v8i16:
   case IceType_v4i32:
     Asm->vandq(Dest, getSrc(0), getSrc(1));
   }
   assert(!Asm->needsTextFixup());
 }
 
+template <> void InstARM32Vceq::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  const Variable *Dest = getDest();
+  const Type SrcTy = getSrc(0)->getType();
+  switch (SrcTy) {
+  default:
+    llvm::report_fatal_error("Vceq not defined on type " +
+                             typeStdString(SrcTy));
+  case IceType_v4i1:
+  case IceType_v8i1:
+  case IceType_v16i1:
+  case IceType_v16i8:
+  case IceType_v8i16:
+  case IceType_v4i32:
+    Asm->vceqqi(typeElementType(SrcTy), Dest, getSrc(0), getSrc(1));
+    break;
+  case IceType_v4f32:
+    Asm->vceqqs(Dest, getSrc(0), getSrc(1));
+    break;
+  }
+  assert(!Asm->needsTextFixup());
+}
+
+template <> void InstARM32Vcge::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  const Variable *Dest = getDest();
+  const Type SrcTy = getSrc(0)->getType();
+  switch (SrcTy) {
+  default:
+    llvm::report_fatal_error("Vcge not defined on type " +
+                             typeStdString(Dest->getType()));
+  case IceType_v4i1:
+  case IceType_v8i1:
+  case IceType_v16i1:
+  case IceType_v16i8:
+  case IceType_v8i16:
+  case IceType_v4i32: {
+    const Type ElmtTy = typeElementType(SrcTy);
+    assert(Sign != InstARM32::FS_None);
+    switch (Sign) {
+    case InstARM32::FS_None: // defaults to unsigned.
+      llvm_unreachable("Sign should not be FS_None.");
+    case InstARM32::FS_Unsigned:
+      Asm->vcugeqi(ElmtTy, Dest, getSrc(0), getSrc(1));
+      break;
+    case InstARM32::FS_Signed:
+      Asm->vcgeqi(ElmtTy, Dest, getSrc(0), getSrc(1));
+      break;
+    }
+  } break;
+  case IceType_v4f32:
+    Asm->vcgeqs(Dest, getSrc(0), getSrc(1));
+    break;
+  }
+}
+
+template <> void InstARM32Vcgt::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  const Variable *Dest = getDest();
+  const Type SrcTy = getSrc(0)->getType();
+  switch (SrcTy) {
+  default:
+    llvm::report_fatal_error("Vcgt not defined on type " +
+                             typeStdString(Dest->getType()));
+  case IceType_v4i1:
+  case IceType_v8i1:
+  case IceType_v16i1:
+  case IceType_v16i8:
+  case IceType_v8i16:
+  case IceType_v4i32: {
+    const Type ElmtTy = typeElementType(SrcTy);
+    assert(Sign != InstARM32::FS_None);
+    switch (Sign) {
+    case InstARM32::FS_None: // defaults to unsigned.
+      llvm_unreachable("Sign should not be FS_None.");
+    case InstARM32::FS_Unsigned:
+      Asm->vcugtqi(ElmtTy, Dest, getSrc(0), getSrc(1));
+      break;
+    case InstARM32::FS_Signed:
+      Asm->vcgtqi(ElmtTy, Dest, getSrc(0), getSrc(1));
+      break;
+    }
+  } break;
+  case IceType_v4f32:
+    Asm->vcgtqs(Dest, getSrc(0), getSrc(1));
+    break;
+  }
+}
+
 template <> void InstARM32Vbsl::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
   switch (Dest->getType()) {
   default:
     llvm::report_fatal_error("Vbsl not defined on type " +
                              typeStdString(Dest->getType()));
   case IceType_v4i1:
   case IceType_v8i1:
   case IceType_v16i1:
@@ skipping 71 matching lines @@
     Asm->vmlss(getDest(), getSrc(1), getSrc(2), CondARM32::AL);
     assert(!Asm->needsTextFixup());
     return;
   case IceType_f64:
     Asm->vmlsd(getDest(), getSrc(1), getSrc(2), CondARM32::AL);
     assert(!Asm->needsTextFixup());
     return;
   }
 }
 
+template <> void InstARM32Vmvn::emitIAS(const Cfg *Func) const {
+  auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
+  const Variable *Dest = getDest();
+  switch (Dest->getType()) {
+  default:
+    llvm::report_fatal_error("Vmvn not defined on type " +
+                             typeStdString(Dest->getType()));
+  case IceType_v4i1:
+  case IceType_v8i1:
+  case IceType_v16i1:
+  case IceType_v16i8:
+  case IceType_v8i16:
+  case IceType_v4i32:
+  case IceType_v4f32: {
+    Asm->vmvnq(Dest, getSrc(0));
+  } break;
+  }
+}
+
 template <> void InstARM32Vneg::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
   const Type DestTy = Dest->getType();
   switch (Dest->getType()) {
   default:
     llvm::report_fatal_error("Vneg not defined on type " +
                              typeStdString(Dest->getType()));
   case IceType_v4i1:
   case IceType_v8i1:
@@ skipping 27 matching lines @@
 }
 
 template <> void InstARM32Vshl::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
   const Type DestTy = Dest->getType();
   switch (DestTy) {
   default:
     llvm::report_fatal_error("Vshl not defined on type " +
                              typeStdString(Dest->getType()));
+  // TODO(jpp): handle i1 vectors in terms of element count instead of element
+  // type.
   case IceType_v4i1:
   case IceType_v8i1:
   case IceType_v16i1:
   case IceType_v16i8:
   case IceType_v8i16:
   case IceType_v4i32: {
     const Type ElmtTy = typeElementType(DestTy);
     assert(Sign != InstARM32::FS_None);
     switch (Sign) {
     case InstARM32::FS_None: // defaults to unsigned.
@@ skipping 17 matching lines @@
 }
 
 template <> void InstARM32Vshr::emitIAS(const Cfg *Func) const {
   auto *Asm = Func->getAssembler<ARM32::AssemblerARM32>();
   const Variable *Dest = getDest();
   const Type DestTy = Dest->getType();
   switch (DestTy) {
   default:
     llvm::report_fatal_error("Vshr not defined on type " +
                              typeStdString(Dest->getType()));
+  // TODO(jpp): handle i1 vectors in terms of element count instead of element
+  // type.
   case IceType_v4i1:
   case IceType_v8i1:
   case IceType_v16i1:
   case IceType_v16i8:
   case IceType_v8i16:
   case IceType_v4i32: {
     const Type ElmtTy = typeElementType(DestTy);
     const auto *Imm6 = llvm::cast<ConstantInteger32>(getSrc(1));
     assert(Sign != InstARM32::FS_None);
     switch (Sign) {
@@ skipping 616 matching lines @@
 template <> const char *InstARM32Rsb::Opcode = "rsb";
 template <> const char *InstARM32Rsc::Opcode = "rsc";
 template <> const char *InstARM32Sbc::Opcode = "sbc";
 template <> const char *InstARM32Sdiv::Opcode = "sdiv";
 template <> const char *InstARM32Sub::Opcode = "sub";
 template <> const char *InstARM32Udiv::Opcode = "udiv";
 // FP
 template <> const char *InstARM32Vadd::Opcode = "vadd";
 template <> const char *InstARM32Vand::Opcode = "vand";
 template <> const char *InstARM32Vbsl::Opcode = "vbsl";
+template <> const char *InstARM32Vceq::Opcode = "vceq";
+template <> const char *InstARM32ThreeAddrFP<InstARM32::Vcge>::Opcode = "vcge";
+template <> const char *InstARM32ThreeAddrFP<InstARM32::Vcgt>::Opcode = "vcgt";
 template <> const char *InstARM32Vdiv::Opcode = "vdiv";
 template <> const char *InstARM32Veor::Opcode = "veor";
 template <> const char *InstARM32Vmla::Opcode = "vmla";
 template <> const char *InstARM32Vmls::Opcode = "vmls";
 template <> const char *InstARM32Vmul::Opcode = "vmul";
+template <> const char *InstARM32Vmvn::Opcode = "vmvn";
 template <> const char *InstARM32Vorr::Opcode = "vorr";
 template <> const char *InstARM32UnaryopFP<InstARM32::Vneg>::Opcode = "vneg";
 template <> const char *InstARM32ThreeAddrFP<InstARM32::Vshl>::Opcode = "vshl";
 template <> const char *InstARM32ThreeAddrFP<InstARM32::Vshr>::Opcode = "vshr";
 template <> const char *InstARM32Vsub::Opcode = "vsub";
 // Four-addr ops
 template <> const char *InstARM32Mla::Opcode = "mla";
 template <> const char *InstARM32Mls::Opcode = "mls";
 // Cmp-like ops
 template <> const char *InstARM32Cmn::Opcode = "cmn";
@@ skipping 218 matching lines @@
       if (const auto *Var = llvm::dyn_cast<Variable>(Src0)) {
         Asm->vmovdd(Dest, Var, Cond);
         return;
       }
       if (const auto *FpImm = llvm::dyn_cast<OperandARM32FlexFpImm>(Src0)) {
         Asm->vmovd(Dest, FpImm, Cond);
         return;
       }
     }
     break; // Error
+  // TODO(jpp): Remove vectors of i1.
   case IceType_v4i1:
   case IceType_v8i1:
   case IceType_v16i1:
   case IceType_v16i8:
   case IceType_v8i16:
   case IceType_v4i32:
   case IceType_v4f32:
     assert(CondARM32::isUnconditional(Cond) &&
            "Moves on vector must be unconditional!");
     if (isVectorType(SrcTy)) {
@@ skipping 1206 matching lines @@
 template class InstARM32ThreeAddrGPR<InstARM32::Mul>;
 template class InstARM32ThreeAddrGPR<InstARM32::Orr>;
 template class InstARM32ThreeAddrGPR<InstARM32::Rsb>;
 template class InstARM32ThreeAddrGPR<InstARM32::Rsc>;
 template class InstARM32ThreeAddrGPR<InstARM32::Sbc>;
 template class InstARM32ThreeAddrGPR<InstARM32::Sdiv>;
 template class InstARM32ThreeAddrGPR<InstARM32::Sub>;
 template class InstARM32ThreeAddrGPR<InstARM32::Udiv>;
 
 template class InstARM32ThreeAddrFP<InstARM32::Vadd>;
+template class InstARM32ThreeAddrSignAwareFP<InstARM32::Vcge>;
+template class InstARM32ThreeAddrSignAwareFP<InstARM32::Vcgt>;
 template class InstARM32ThreeAddrFP<InstARM32::Vdiv>;
 template class InstARM32ThreeAddrFP<InstARM32::Veor>;
 template class InstARM32FourAddrFP<InstARM32::Vmla>;
 template class InstARM32FourAddrFP<InstARM32::Vmls>;
 template class InstARM32ThreeAddrFP<InstARM32::Vmul>;
 template class InstARM32UnaryopSignAwareFP<InstARM32::Vneg>;
 template class InstARM32ThreeAddrSignAwareFP<InstARM32::Vshl>;
 template class InstARM32ThreeAddrSignAwareFP<InstARM32::Vshr>;
 template class InstARM32ThreeAddrFP<InstARM32::Vsub>;
 
@@ skipping 13 matching lines @@
 
 template class InstARM32FourAddrGPR<InstARM32::Mla>;
 template class InstARM32FourAddrGPR<InstARM32::Mls>;
 
 template class InstARM32CmpLike<InstARM32::Cmn>;
 template class InstARM32CmpLike<InstARM32::Cmp>;
 template class InstARM32CmpLike<InstARM32::Tst>;
 
 } // end of namespace ARM32
 } // end of namespace Ice