Subzero. ARM32. De-scalarizes icmp and fcmp for vectors.

src/DartARM32/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
 // Please update the (git) revision if we merge changes from Dart.
 // https://code.google.com/p/dart/wiki/GettingTheSource
 
 #include "vm/globals.h"  // NOLINT
 #if defined(TARGET_ARCH_ARM)
@@ skipping 1305 matching lines @@
 
 void Assembler::vornq(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B21 | B20 | B8 | B4, kByte, qd, qn, qm);
 }
 
 #if 0
 // Moved to ARM32::AssemblerARM32::vandq()
 void Assembler::vandq(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B8 | B4, kByte, qd, qn, qm);
 }
-#endif
 
 void Assembler::vmvnq(QRegister qd, QRegister qm) {
   EmitSIMDqqq(B25 | B24 | B23 | B10 | B8 | B7, kWordPair, qd, Q0, qm);
 }
+#endif
 
 
 void Assembler::vminqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B21 | B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
 }
 
 
 void Assembler::vmaxqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
 }
@@ skipping 74 matching lines @@
   ASSERT((len >= 1) && (len <= 4));
   EmitSIMDddd(B24 | B23 | B11 | ((len - 1) * B8), kWordPair, dd, dn, dm);
 }
 
 
 void Assembler::vzipqw(QRegister qd, QRegister qm) {
   EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B8 | B7, kByte, qd, Q0, qm);
 }
 
 
+#if 0
+// Moved to Arm32::AssemblerARM32::vceqqi().
 void Assembler::vceqqi(OperandSize sz,
                       QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11 | B4, sz, qd, qn, qm);
 }
 
-
+// Moved to Arm32::AssemblerARM32::vceqqi().
 void Assembler::vceqqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B9, kSWord, qd, qn, qm);
 }
 
-
+// Moved to Arm32::AssemblerARM32::vcgeqi().
 void Assembler::vcgeqi(OperandSize sz,
                       QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B9 | B8 | B4, sz, qd, qn, qm);
 }
 
-
+// Moved to Arm32::AssemblerARM32::vcugeqi().
 void Assembler::vcugeqi(OperandSize sz,
                       QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B9 | B8 | B4, sz, qd, qn, qm);
 }
 
-
+// Moved to Arm32::AssemblerARM32::vcgeqs().
 void Assembler::vcgeqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11 | B10 | B9, kSWord, qd, qn, qm);
 }
 
-
+// Moved to Arm32::AssemblerARM32::vcgtqi().
 void Assembler::vcgtqi(OperandSize sz,
                       QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B9 | B8, sz, qd, qn, qm);
 }
 
-
+// Moved to Arm32::AssemblerARM32::vcugtqi().
 void Assembler::vcugtqi(OperandSize sz,
                       QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B9 | B8, sz, qd, qn, qm);
 }
 
-
+// Moved to Arm32::AssemblerARM32::vcgtqs().
 void Assembler::vcgtqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B21 | B11 | B10 | B9, kSWord, qd, qn, qm);
 }
 
-
-#if 0
 // Moved to ARM32::AssemblerARM32::bkpt()
 void Assembler::bkpt(uint16_t imm16) {
   Emit(BkptEncoding(imm16));
 }
 #endif
 
 
 void Assembler::b(Label* label, Condition cond) {
   EmitBranch(cond, label, false);
 }
@@ skipping 2213 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM