| Index: src/compiler/arm/instruction-selector-arm.cc
|
| diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc
|
| index ef0bb6800e4933ecf905a65f3ca03558760db289..8d11c1d82647a98a63146f29db11e568097f5449 100644
|
| --- a/src/compiler/arm/instruction-selector-arm.cc
|
| +++ b/src/compiler/arm/instruction-selector-arm.cc
|
| @@ -1814,6 +1814,29 @@ void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) {
|
| g.UseRegister(right));
|
| }
|
|
|
| +void InstructionSelector::VisitAtomicLoad(Node* node) {
|
| + LoadRepresentation load_rep = LoadRepresentationOf(node->op());
|
| + ArmOperandGenerator g(this);
|
| + Node* base = node->InputAt(0);
|
| + Node* index = node->InputAt(1);
|
| + ArchOpcode opcode = kArchNop;
|
| + switch (load_rep.representation()) {
|
| + case MachineRepresentation::kWord8:
|
| + opcode = load_rep.IsSigned() ? kAtomicLoadInt8 : kAtomicLoadUint8;
|
| + break;
|
| + case MachineRepresentation::kWord16:
|
| + opcode = load_rep.IsSigned() ? kAtomicLoadInt16 : kAtomicLoadUint16;
|
| + break;
|
| + case MachineRepresentation::kWord32:
|
| + opcode = kAtomicLoadWord32;
|
| + break;
|
| + default:
|
| + UNREACHABLE();
|
| + return;
|
| + }
|
| + Emit(opcode | AddressingModeField::encode(kMode_Offset_RR),
|
| + g.DefineAsRegister(node), g.UseRegister(base), g.UseRegister(index));
|
| +}
|
|
|
| // static
|
| MachineOperatorBuilder::Flags
|
|
|