[Atomics] Remove Atomics code stubs; use TF ops

src/compiler/arm64/code-generator-arm64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/arm64/frames-arm64.h"
 #include "src/arm64/macro-assembler-arm64.h"
 #include "src/ast/scopes.h"
 #include "src/compiler/code-generator-impl.h"
@@ skipping 454 matching lines @@
       __ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0),    \
                    i.InputRegister##width(1));                              \
     } else {                                                                \
       uint32_t imm =                                                        \
           static_cast<uint32_t>(i.InputOperand##width(1).ImmediateValue()); \
       __ asm_instr(i.OutputRegister##width(), i.InputRegister##width(0),    \
                    imm % (width));                                          \
     }                                                                       \
   } while (0)
 
+#define ASSEMBLE_ATOMIC_LOAD_INTEGER(asm_instr)                       \
+  do {                                                                \
+    __ asm_instr(i.OutputRegister(),                                  \
+                 MemOperand(i.InputRegister(0), i.InputRegister(1))); \
+    __ Dmb(InnerShareable, BarrierAll);                               \
+  } while (0)
+
 void CodeGenerator::AssembleDeconstructFrame() {
   const CallDescriptor* descriptor = linkage()->GetIncomingDescriptor();
   if (descriptor->IsCFunctionCall() || descriptor->UseNativeStack()) {
     __ Mov(csp, fp);
   } else {
     __ Mov(jssp, fp);
   }
   __ Pop(fp, lr);
 }
 
@@ skipping 912 matching lines @@
       break;
     case kCheckedStoreWord64:
       ASSEMBLE_CHECKED_STORE_INTEGER_64(Str);
       break;
     case kCheckedStoreFloat32:
       ASSEMBLE_CHECKED_STORE_FLOAT(32);
       break;
     case kCheckedStoreFloat64:
       ASSEMBLE_CHECKED_STORE_FLOAT(64);
       break;
+    case kAtomicLoadInt8:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(Ldrsb);
+      break;
+    case kAtomicLoadUint8:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(Ldrb);
+      break;
+    case kAtomicLoadInt16:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(Ldrsh);
+      break;
+    case kAtomicLoadUint16:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(Ldrh);
+      break;
+    case kAtomicLoadWord32:
+      ASSEMBLE_ATOMIC_LOAD_INTEGER(Ldr);

[Rodolph Perfetta, 2016/04/15 14:36:03]

For Ldrb/sb/h/sh the amount of data loaded is given by the mnemonic, for Ldr it
will depend on the size of the target register and here you are using a 64-bit
one not 32-bit.

[binji, 2016/04/15 21:00:13]

Oops, right. Done

+      break;
   }
 }  // NOLINT(readability/fn_size)
 
 
 // Assemble branches after this instruction.
 void CodeGenerator::AssembleArchBranch(Instruction* instr, BranchInfo* branch) {
   Arm64OperandConverter i(this, instr);
   Label* tlabel = branch->true_label;
   Label* flabel = branch->false_label;
   FlagsCondition condition = branch->condition;
@@ skipping 397 matching lines @@
       padding_size -= kInstructionSize;
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8