Subzero, Wasm: Link and run torture tests; bug fixes.

src/IceCfg.cpp

 //===- subzero/src/IceCfg.cpp - Control flow graph implementation ---------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 243 matching lines @@
       assert(Phi);
       for (SizeT i = 0; i < InEdges.size(); ++i) {
         Phi->setLabel(i, InEdges[i]);
       }
     }
   }
 }
 
 void Cfg::computeInOutEdges() {
   // Compute the out-edges.
-  for (CfgNode *Node : Nodes)
+  for (CfgNode *Node : Nodes) {
     Node->computeSuccessors();
+  }
 
   // Prune any unreachable nodes before computing in-edges.
   SizeT NumNodes = getNumNodes();
   BitVector Reachable(NumNodes);
   BitVector Pending(NumNodes);
   Pending.set(getEntryNode()->getIndex());
   while (true) {
     int Index = Pending.find_first();
     if (Index == -1)
       break;
@@ skipping 316 matching lines @@
     // Allocate the fixed area in the function prolog.
     getTarget()->reserveFixedAllocaArea(TotalSize, CombinedAlignment);
   } break;
   }
 }
 
 void Cfg::processAllocas(bool SortAndCombine) {
   TimerMarker _(TimerStack::TT_alloca, this);
   const uint32_t StackAlignment = getTarget()->getStackAlignment();
   CfgNode *EntryNode = getEntryNode();
+  assert(EntryNode);
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(StackAlignment));
   // Determine if there are large alignment allocations in the entry block or
   // dynamic allocations (variable size in the entry block).
   bool HasLargeAlignment = false;
   bool HasDynamicAllocation = false;
   for (Inst &Instr : EntryNode->getInsts()) {
     if (auto *Alloca = llvm::dyn_cast<InstAlloca>(&Instr)) {
       uint32_t AlignmentParam = Alloca->getAlignInBytes();
       if (AlignmentParam > StackAlignment)
@@ skipping 553 matching lines @@
     }
   }
   // Print each basic block
   for (CfgNode *Node : Nodes)
     Node->dump(this);
   if (isVerbose(IceV_Instructions))
     Str << "}\n";
 }
 
 } // end of namespace Ice